Commit cd5103ee authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Jani Nikula
Browse files

drm/i915/display/hdmi: use intel_de_rmw if possible 



The helper makes the code more compact and readable.

Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230105131046.2173431-6-andrzej.hajda@intel.com
parent 1e116253

drivers/gpu/drm/i915/display/g4x_hdmi.c

+4 −4
Original line number Diff line number Diff line
@@ -273,8 +273,8 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, 
	 */



	if (pipe_config->pipe_bpp > 24) {

		intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),

			       intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),

			     0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);



		temp &= ~SDVO_COLOR_FORMAT_MASK;

		temp |= SDVO_COLOR_FORMAT_8bpc;
@@ -290,8 +290,8 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, 
		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);

		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);



		intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),

			       intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),

			     TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);

	}



	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&

drivers/gpu/drm/i915/display/intel_hdcp.c

+6 −9
Original line number Diff line number Diff line
@@ -943,8 +943,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) 


	repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,

						   port);

	intel_de_write(dev_priv, HDCP_REP_CTL,

		       intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl);

	intel_de_rmw(dev_priv, HDCP_REP_CTL, repeater_ctl, 0);



	ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false);

	if (ret) {
@@ -1819,12 +1818,10 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) 
	}



	if (intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &

	    LINK_AUTH_STATUS) {

	    LINK_AUTH_STATUS)

		/* Link is Authenticated. Now set for Encryption */

		intel_de_write(dev_priv,

			       HDCP2_CTL(dev_priv, cpu_transcoder, port),

			       intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) | CTL_LINK_ENCRYPTION_REQ);

	}

		intel_de_rmw(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),

			     0, CTL_LINK_ENCRYPTION_REQ);



	ret = intel_de_wait_for_set(dev_priv,

				    HDCP2_STATUS(dev_priv, cpu_transcoder,
@@ -1848,8 +1845,8 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) 
	drm_WARN_ON(&dev_priv->drm, !(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &

				      LINK_ENCRYPTION_STATUS));



	intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),

		       intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ);

	intel_de_rmw(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),

		     CTL_LINK_ENCRYPTION_REQ, 0);



	ret = intel_de_wait_for_clear(dev_priv,

				      HDCP2_STATUS(dev_priv, cpu_transcoder,

drivers/gpu/drm/i915/display/intel_hdmi.c

+12 −28
Original line number Diff line number Diff line
@@ -238,15 +238,11 @@ static void g4x_read_infoframe(struct intel_encoder *encoder, 
			       void *frame, ssize_t len)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 val, *data = frame;

	u32 *data = frame;

	int i;



	val = intel_de_read(dev_priv, VIDEO_DIP_CTL);



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(type);



	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);

	intel_de_rmw(dev_priv, VIDEO_DIP_CTL,

		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));



	for (i = 0; i < len; i += 4)

		*data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
@@ -314,15 +310,11 @@ static void ibx_read_infoframe(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	u32 val, *data = frame;

	u32 *data = frame;

	int i;



	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(type);



	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);

	intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),

		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));



	for (i = 0; i < len; i += 4)

		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
@@ -396,15 +388,11 @@ static void cpt_read_infoframe(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	u32 val, *data = frame;

	u32 *data = frame;

	int i;



	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(type);



	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);

	intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),

		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));



	for (i = 0; i < len; i += 4)

		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
@@ -472,15 +460,11 @@ static void vlv_read_infoframe(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	u32 val, *data = frame;

	u32 *data = frame;

	int i;



	val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(type);



	intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);

	intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe),

		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));



	for (i = 0; i < len; i += 4)

		*data++ = intel_de_read(dev_priv,