Commit cd4e5f30 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b 



This adds the regulator node to the quartz64-b device tree,
and enables the PCIe 2 controller and combphy for it.

Signed-off-by: default avatarNicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20220718033145.792657-1-frattaroli.nicolas@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 523adb55

arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts

+34 −0
Original line number Diff line number Diff line
@@ -69,6 +69,18 @@ 
		power-off-delay-us = <5000000>;

	};



	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {

		compatible = "regulator-fixed";

		enable-active-high;

		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&pcie_enable_h>;

		regulator-name = "vcc3v3_pcie_p";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc_3v3>;

	};



	vcc5v0_in: vcc5v0-in-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc5v0_in";
@@ -128,6 +140,10 @@ 
	status = "okay";

};



&combphy2 {

	status = "okay";

};



&cpu0 {

	cpu-supply = <&vdd_cpu>;

};
@@ -457,6 +473,14 @@ 
	};

};



&pcie2x1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_reset_h>;

	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;

	vpcie3v3-supply = <&vcc3v3_pcie_p>;

	status = "okay";

};



&pinctrl {

	bt {

		bt_enable_h: bt-enable-h {
@@ -478,6 +502,16 @@ 
		};

	};



	pcie {

		pcie_enable_h: pcie-enable-h {

			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;

		};



		pcie_reset_h: pcie-reset-h {

			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	pmic {

		pmic_int: pmic_int {

			rockchip,pins =