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Commit cd4d6f35 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
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clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 



Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3dcbd36f
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