Commit cd427485 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote-tracking branch 'scott/next' into next 

Freescale updates from Scott. Mostly support for critical
and machine check exceptions on 64-bit BookE, some new
PCI suspend/resume work and misc bits.
parents d410ae21 48b16180

Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt

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Freescale L2 Cache Controller



L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.

The cache bindings explained below are ePAPR compliant



Required Properties:



- compatible	: Should include "fsl,chip-l2-cache-controller" and "cache"

		  where chip is the processor (bsc9132, npc8572 etc.)

- reg		: Address and size of L2 cache controller registers

- cache-size	: Size of the entire L2 cache

- interrupts	: Error interrupt of L2 controller

- cache-line-size : Size of L2 cache lines



Example:



	L2: l2-cache-controller@20000 {

		compatible = "fsl,bsc9132-l2-cache-controller", "cache";

		reg = <0x20000 0x1000>;

		cache-line-size = <32>; // 32 bytes

		cache-size = <0x40000>; // L2,256K

		interrupts = <16 2 1 0>;

	};

Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt

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Freescale DDR memory controller



Properties:



- compatible	: Should include "fsl,chip-memory-controller" where

		  chip is the processor (bsc9132, mpc8572 etc.), or

		  "fsl,qoriq-memory-controller".

- reg		: Address and size of DDR controller registers

- interrupts	: Error interrupt of DDR controller



Example 1:



	memory-controller@2000 {

		compatible = "fsl,bsc9132-memory-controller";

		reg = <0x2000 0x1000>;

		interrupts = <16 2 1 8>;

	};





Example 2:



	ddr1: memory-controller@8000 {

		compatible = "fsl,qoriq-memory-controller-v4.7",

				"fsl,qoriq-memory-controller";

		reg = <0x8000 0x1000>;

		interrupts = <16 2 1 23>;

	};

Documentation/devicetree/bindings/usb/fsl-usb.txt

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@@ -8,7 +8,9 @@ and additions : 
Required properties :

 - compatible : Should be "fsl-usb2-mph" for multi port host USB

   controllers, or "fsl-usb2-dr" for dual role USB controllers

   or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121

   or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.

   Wherever applicable, the IP version of the USB controller should

   also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).

 - phy_type : For multi port host USB controllers, should be one of

   "ulpi", or "serial". For dual role USB controllers, should be

   one of "ulpi", "utmi", "utmi_wide", or "serial".

arch/powerpc/boot/dts/fsl/b4420si-post.dtsi

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@@ -86,6 +86,42 @@ 


	clockgen: global-utilities@e1000 {

		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";

		ranges = <0x0 0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-2.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2", "pll0-div4";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2", "pll1-div4";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-2.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,

				<&pll1 0>, <&pll1 1>, <&pll1 2>;

			clock-names = "pll0", "pll0-div2", "pll0-div4",

				"pll1", "pll1-div2", "pll1-div4";

			clock-output-names = "cmux0";

		};

	};



	rcpm: global-utilities@e2000 {

arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

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		cpu0: PowerPC,e6500@0 {

			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

	};