Commit cd3eb7ef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull iommu updates from Joerg Roedel:

 - SMMU Updates from Will Deacon:

     - SMMUv3:
        - Support stalling faults for platform devices
        - Decrease defaults sizes for the event and PRI queues
     - SMMUv2:
        - Support for a new '->probe_finalize' hook, needed by Nvidia
        - Even more Qualcomm compatible strings
        - Avoid Adreno TTBR1 quirk for DB820C platform

 - Intel VT-d updates from Lu Baolu:

     - Convert Intel IOMMU to use sva_lib helpers in iommu core
     - ftrace and debugfs supports for page fault handling
     - Support asynchronous nested capabilities
     - Various misc cleanups

 - Support for new VIOT ACPI table to make the VirtIO IOMMU
   available on x86

 - Add the amd_iommu=force_enable command line option to enable
   the IOMMU on platforms where they are known to cause problems

 - Support for version 2 of the Rockchip IOMMU

 - Various smaller fixes, cleanups and refactorings

* tag 'iommu-updates-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (66 commits)
  iommu/virtio: Enable x86 support
  iommu/dma: Pass address limit rather than size to iommu_setup_dma_ops()
  ACPI: Add driver for the VIOT table
  ACPI: Move IOMMU setup code out of IORT
  ACPI: arm64: Move DMA setup operations out of IORT
  iommu/vt-d: Fix dereference of pointer info before it is null checked
  iommu: Update "iommu.strict" documentation
  iommu/arm-smmu: Check smmu->impl pointer before dereferencing
  iommu/arm-smmu-v3: Remove unnecessary oom message
  iommu/arm-smmu: Fix arm_smmu_device refcount leak in address translation
  iommu/arm-smmu: Fix arm_smmu_device refcount leak when arm_smmu_rpm_get fails
  iommu/vt-d: Fix linker error on 32-bit
  iommu/vt-d: No need to typecast
  iommu/vt-d: Define counter explicitly as unsigned int
  iommu/vt-d: Remove unnecessary braces
  iommu/vt-d: Removed unused iommu_count in dmar domain
  iommu/vt-d: Use bitfields for DMAR capabilities
  iommu/vt-d: Use DEVICE_ATTR_RO macro
  iommu/vt-d: Fix out-bounds-warning in intel/svm.c
  iommu/vt-d: Add PRQ handling latency sampling
  ...
parents 35e43538 2b9d8e3e

Documentation/admin-guide/kernel-parameters.txt

+8 −1
Original line number Diff line number Diff line
@@ -301,6 +301,9 @@ 
					  allowed anymore to lift isolation

					  requirements as needed. This option

					  does not override iommu=pt

			force_enable - Force enable the IOMMU on platforms known

				       to be buggy with IOMMU enabled. Use this

				       option with care.



	amd_iommu_dump=	[HW,X86-64]

			Enable AMD IOMMU driver option to dump the ACPI table
@@ -2031,7 +2034,7 @@ 
			  forcing Dual Address Cycle for PCI cards supporting

			  greater than 32-bit addressing.



	iommu.strict=	[ARM64] Configure TLB invalidation behaviour

	iommu.strict=	[ARM64, X86] Configure TLB invalidation behaviour

			Format: { "0" | "1" }

			0 - Lazy mode.

			  Request that DMA unmap operations use deferred
@@ -2042,6 +2045,10 @@ 
			1 - Strict mode (default).

			  DMA unmap operations invalidate IOMMU hardware TLBs

			  synchronously.

			Note: on x86, the default behaviour depends on the

			equivalent driver-specific parameters, but a strict

			mode explicitly specified by either method takes

			precedence.



	iommu.passthrough=

			[ARM64, X86] Configure DMA to bypass the IOMMU by default.

Documentation/devicetree/bindings/iommu/iommu.txt

+18 −0
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@@ -92,6 +92,24 @@ Optional properties: 
  tagging DMA transactions with an address space identifier. By default,

  this is 0, which means that the device only has one address space.



- dma-can-stall: When present, the master can wait for a transaction to

  complete for an indefinite amount of time. Upon translation fault some

  IOMMUs, instead of aborting the translation immediately, may first

  notify the driver and keep the transaction in flight. This allows the OS

  to inspect the fault and, for example, make physical pages resident

  before updating the mappings and completing the transaction. Such IOMMU

  accepts a limited number of simultaneous stalled transactions before

  having to either put back-pressure on the master, or abort new faulting

  transactions.



  Firmware has to opt-in stalling, because most buses and masters don't

  support it. In particular it isn't compatible with PCI, where

  transactions have to complete before a time limit. More generally it

  won't work in systems and masters that haven't been designed for

  stalling. For example the OS, in order to handle a stalled transaction,

  may attempt to retrieve pages from secondary storage in a stalled

  domain, leading to a deadlock.





Notes:

======

Documentation/devicetree/bindings/iommu/rockchip,iommu.txt

deleted100644 → 0
+0 −38
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Rockchip IOMMU

==============



A Rockchip DRM iommu translates io virtual addresses to physical addresses for

its master device.  Each slave device is bound to a single master device, and

shares its clocks, power domain and irq.



Required properties:

- compatible      : Should be "rockchip,iommu"

- reg             : Address space for the configuration registers

- interrupts      : Interrupt specifier for the IOMMU instance

- interrupt-names : Interrupt name for the IOMMU instance

- #iommu-cells    : Should be <0>.  This indicates the iommu is a

                    "single-master" device, and needs no additional information

                    to associate with its master device.  See:

                    Documentation/devicetree/bindings/iommu/iommu.txt

- clocks          : A list of clocks required for the IOMMU to be accessible by

                    the host CPU.

- clock-names     : Should contain the following:

	"iface" - Main peripheral bus clock (PCLK/HCL) (required)

	"aclk"  - AXI bus clock (required)



Optional properties:

- rockchip,disable-mmu-reset : Don't use the mmu reset operation.

			       Some mmu instances may produce unexpected results

			       when the reset operation is used.



Example:



	vopl_mmu: iommu@ff940300 {

		compatible = "rockchip,iommu";

		reg = <0xff940300 0x100>;

		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vopl_mmu";

		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;

		clock-names = "aclk", "iface";

		#iommu-cells = <0>;

	};

Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml

0 → 100644
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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip IOMMU



maintainers:

  - Heiko Stuebner <heiko@sntech.de>



description: |+

  A Rockchip DRM iommu translates io virtual addresses to physical addresses for

  its master device. Each slave device is bound to a single master device and

  shares its clocks, power domain and irq.



  For information on assigning IOMMU controller to its peripheral devices,

  see generic IOMMU bindings.



properties:

  compatible:

    enum:

      - rockchip,iommu

      - rockchip,rk3568-iommu



  reg:

    items:

      - description: configuration registers for MMU instance 0

      - description: configuration registers for MMU instance 1

    minItems: 1

    maxItems: 2



  interrupts:

    items:

      - description: interruption for MMU instance 0

      - description: interruption for MMU instance 1

    minItems: 1

    maxItems: 2



  clocks:

    items:

      - description: Core clock

      - description: Interface clock



  clock-names:

    items:

      - const: aclk

      - const: iface



  "#iommu-cells":

    const: 0



  power-domains:

    maxItems: 1



  rockchip,disable-mmu-reset:

    $ref: /schemas/types.yaml#/definitions/flag

    description: |

      Do not use the mmu reset operation.

      Some mmu instances may produce unexpected results

      when the reset operation is used.



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#iommu-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/rk3399-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    vopl_mmu: iommu@ff940300 {

      compatible = "rockchip,iommu";

      reg = <0xff940300 0x100>;

      interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;

      clock-names = "aclk", "iface";

      #iommu-cells = <0>;

    };

MAINTAINERS

+8 −0
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@@ -431,6 +431,14 @@ W: https://01.org/linux-acpi 
B:	https://bugzilla.kernel.org

F:	drivers/acpi/acpi_video.c









ACPI VIOT DRIVER









M:	Jean-Philippe Brucker <jean-philippe@linaro.org>









L:	linux-acpi@vger.kernel.org









L:	iommu@lists.linux-foundation.org









S:	Maintained









F:	drivers/acpi/viot.c









F:	include/linux/acpi_viot.h

















ACPI WMI DRIVER









L:	platform-driver-x86@vger.kernel.org









S:	Orphan