Commit cd35bf9d authored by Christoph Niedermaier's avatar Christoph Niedermaier Committed by Shawn Guo
Browse files

ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl 



The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to
the SoM devicetree. Add PCIe Reset GPIO to the board devicetree.

Signed-off-by: default avatarChristoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e0dff0fe

arch/arm/boot/dts/imx6q-dhcom-pdk2.dts

+3 −4
Original line number Diff line number Diff line
@@ -232,9 +232,9 @@ 
		>;

	};



	pinctrl_pcie: pcie-grp {

	pinctrl_pcie_reset: pcie-reset-grp {

		fsl,pins = <

			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1

			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0

		>;

	};

};
@@ -244,8 +244,7 @@ 
};



&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie>;

	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;

	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;

	status = "okay";

};

arch/arm/boot/dts/imx6q-dhcom-som.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -450,6 +450,12 @@ 
		>;

	};



	pinctrl_pcie: pcie-grp {

		fsl,pins = <

			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */

		>;

	};



	pinctrl_uart1: uart1-grp {

		fsl,pins = <

			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
@@ -568,6 +574,11 @@ 
	};

};



&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie>;

};



&reg_arm {

	vin-supply = <&sw3_reg>;

};