Commit cd2715b7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_urgent_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC fixes from Borislav Petkov:

 - Relax the condition under which the DIMM label in ghes_edac is set in
   order to accomodate an HPE BIOS which sets only the device but not
   the bank

 - Two forgotten fixes to synopsys_edac when handling error interrupts

* tag 'edac_urgent_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/ghes: Set the DIMM label unconditionally
  EDAC/synopsys: Re-enable the error interrupts on v3 hw
  EDAC/synopsys: Use the correct register to disable the error interrupt on v3 hw
parents 6a010258 5e2805d5

drivers/edac/ghes_edac.c

+8 −3
Original line number Diff line number Diff line
@@ -103,9 +103,14 @@ static void dimm_setup_label(struct dimm_info *dimm, u16 handle) 


	dmi_memdev_name(handle, &bank, &device);



	/* both strings must be non-zero */

	if (bank && *bank && device && *device)

		snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);

	/*

	 * Set to a NULL string when both bank and device are zero. In this case,

	 * the label assigned by default will be preserved.

	 */

	snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",

		 (bank && *bank) ? bank : "",

		 (bank && *bank && device && *device) ? " " : "",

		 (device && *device) ? device : "");

}



static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)

drivers/edac/synopsys_edac.c

+25 −19
Original line number Diff line number Diff line
@@ -514,6 +514,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) 
	memset(p, 0, sizeof(*p));

}



static void enable_intr(struct synps_edac_priv *priv)

{

	/* Enable UE/CE Interrupts */

	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)

		writel(DDR_UE_MASK | DDR_CE_MASK,

		       priv->baseaddr + ECC_CLR_OFST);

	else

		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,

		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);



}



static void disable_intr(struct synps_edac_priv *priv)

{

	/* Disable UE/CE Interrupts */

	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)

		writel(0x0, priv->baseaddr + ECC_CLR_OFST);

	else

		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,

		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);

}



/**

 * intr_handler - Interrupt Handler for ECC interrupts.

 * @irq:        IRQ number.
@@ -555,6 +577,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id) 
	/* v3.0 of the controller does not have this register */

	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))

		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);

	else

		enable_intr(priv);



	return IRQ_HANDLED;

}
@@ -837,25 +862,6 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) 
	init_csrows(mci);

}



static void enable_intr(struct synps_edac_priv *priv)

{

	/* Enable UE/CE Interrupts */

	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)

		writel(DDR_UE_MASK | DDR_CE_MASK,

		       priv->baseaddr + ECC_CLR_OFST);

	else

		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,

		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);



}



static void disable_intr(struct synps_edac_priv *priv)

{

	/* Disable UE/CE Interrupts */

	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,

			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);

}



static int setup_irq(struct mem_ctl_info *mci,

		     struct platform_device *pdev)

{