Loading arch/arm/boot/dts/exynos4412.dtsi +389 −383 Original line number Diff line number Diff line Loading @@ -147,6 +147,9 @@ }; }; soc: soc { pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; Loading Loading @@ -228,7 +231,8 @@ reg = <0x10048000 0x1000>; #clock-cells = <1>; power-domains = <&pd_isp>; clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; clock-names = "aclk200", "aclk400_mcuisp"; }; Loading @@ -244,7 +248,8 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, <1 &combiner 12 5>, <2 &combiner 12 6>, <3 &combiner 12 7>, Loading Loading @@ -547,6 +552,7 @@ }; }; }; }; &combiner { samsung,combiner-nr = <20>; Loading Loading
arch/arm/boot/dts/exynos4412.dtsi +389 −383 Original line number Diff line number Diff line Loading @@ -147,6 +147,9 @@ }; }; soc: soc { pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; Loading Loading @@ -228,7 +231,8 @@ reg = <0x10048000 0x1000>; #clock-cells = <1>; power-domains = <&pd_isp>; clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; clock-names = "aclk200", "aclk400_mcuisp"; }; Loading @@ -244,7 +248,8 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, <1 &combiner 12 5>, <2 &combiner 12 6>, <3 &combiner 12 7>, Loading Loading @@ -547,6 +552,7 @@ }; }; }; }; &combiner { samsung,combiner-nr = <20>; Loading