Commit cd0fcf5a authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP 



Matter of taste. STEP matches the enums.

Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/cf2dccd1c9c7fdcf5de08ea10a9265292b45d8c7.1616764798.git.jani.nikula@intel.com
parent 34b7e27b

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -5333,7 +5333,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 


	if (IS_ALDERLAKE_S(dev_priv) ||

	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||

	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))

	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

		/* Wa_1409767108:tgl,dg1,adl-s */

		table = wa_1409767108_buddy_page_masks;

	else

drivers/gpu/drm/i915/display/intel_psr.c

+2 −2
Original line number Diff line number Diff line
@@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 


	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		/* WA 1408330847 */

		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||

		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||

		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))

			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1109,7 +1109,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 


	/* WA 1408330847 */

	if (intel_dp->psr.psr2_sel_fetch_enabled &&

	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||

	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||

	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))

		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -1858,7 +1858,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, 
{

	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */

	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||

	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))

	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))

		return false;



	return plane_id < PLANE_SPRITE4;

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −5
Original line number Diff line number Diff line
@@ -1093,19 +1093,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
	gen12_gt_workarounds_init(i915, wal);



	/* Wa_1409420604:tgl */

	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))

	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))

		wa_write_or(wal,

			    SUBSLICE_UNIT_LEVEL_CLKGATE2,

			    CPSSUNIT_CLKGATE_DIS);



	/* Wa_1607087056:tgl also know as BUG:1409180338 */

	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))

	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))

		wa_write_or(wal,

			    SLICE_UNIT_LEVEL_CLKGATE,

			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);



	/* Wa_1408615072:tgl[a0] */

	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))

	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))

		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,

			    VSUNIT_CLKGATE_DIS_TGL);

}
@@ -1583,7 +1583,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
	struct drm_i915_private *i915 = engine->i915;



	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||

	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {

	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {

		/*

		 * Wa_1607138336:tgl[a0],dg1[a0]

		 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1593,7 +1593,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);

	}



	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {

	if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {

		/*

		 * Wa_1606679103:tgl

		 * (see also Wa_1606682166:icl)

drivers/gpu/drm/i915/i915_drv.h

+5 −5
Original line number Diff line number Diff line
@@ -1502,15 +1502,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define IS_JSL_EHL_REVID(p, since, until) \

	(IS_JSL_EHL(p) && IS_REVID(p, since, until))



#define IS_TGL_DISP_STEPPING(__i915, since, until) \

#define IS_TGL_DISPLAY_STEP(__i915, since, until) \

	(IS_TIGERLAKE(__i915) && \

	 IS_DISPLAY_STEP(__i915, since, until))



#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \

#define IS_TGL_UY_GT_STEP(__i915, since, until) \

	((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \

	 IS_GT_STEP(__i915, since, until))



#define IS_TGL_GT_STEPPING(__i915, since, until) \

#define IS_TGL_GT_STEP(__i915, since, until) \

	(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \

	 IS_GT_STEP(__i915, since, until))
@@ -1527,11 +1527,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define IS_DG1_REVID(p, since, until) \

	(IS_DG1(p) && IS_REVID(p, since, until))



#define IS_ADLS_DISP_STEPPING(__i915, since, until) \

#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \

	(IS_ALDERLAKE_S(__i915) && \

	 IS_DISPLAY_STEP(__i915, since, until))



#define IS_ADLS_GT_STEPPING(__i915, since, until) \

#define IS_ADLS_GT_STEP(__i915, since, until) \

	(IS_ALDERLAKE_S(__i915) && \

	 IS_GT_STEP(__i915, since, until))