Commit ccfa2466 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Ulf Hansson
Browse files

dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" 



Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.

Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-1-dinguyen@kernel.org


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 63abdf72

Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml

+29 −3
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: Synopsys Designware Mobile Storage Host Controller Binding



allOf:

  - $ref: "synopsys-dw-mshc-common.yaml#"



maintainers:

  - Ulf Hansson <ulf.hansson@linaro.org>
@@ -38,6 +35,35 @@ properties: 
      - const: biu

      - const: ciu



  altr,sysmgr-syscon:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to the sysmgr node

          - description: register offset that controls the SDMMC clock phase

          - description: register shift for the smplsel(drive in) setting

    description:

      This property is optional. Contains the phandle to System Manager block

      that contains the SDMMC clock-phase control register. The first value is

      the pointer to the sysmgr, the 2nd value is the register offset for the

      SDMMC clock phase register, and the 3rd value is the bit shift for the

      smplsel(drive in) setting.



allOf:

  - $ref: synopsys-dw-mshc-common.yaml#



  - if:

      properties:

        compatible:

          contains:

            const: altr,socfpga-dw-mshc

    then:

      properties:

        altr,sysmgr-syscon: true

    else:

      properties:

        altr,sysmgr-syscon: false



required:

  - compatible

  - reg