Commit ccf34586 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.17-2022-01-19' of... 

Merge tag 'amd-drm-fixes-5.17-2022-01-19' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-fixes-5.17-2022-01-19:

amdgpu:
- SR-IOV fix
- VCN harvest fix
- Suspend/resume fixes
- Tahiti fix
- Enable GPU recovery on yellow carp

radeon:
- Fix error handling regression in radeon_driver_open_kms

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120013547.5649-1-alexander.deucher@amd.com
parents 410482b5 4722f463

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+18 −27
Original line number Diff line number Diff line
@@ -2354,7 +2354,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
	}



	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_exchange_data(adev);

		amdgpu_virt_init_data_exchange(adev);



	r = amdgpu_ib_pool_init(adev);

	if (r) {
@@ -4450,33 +4450,24 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) 


	if (amdgpu_gpu_recovery == -1) {

		switch (adev->asic_type) {

		case CHIP_BONAIRE:

		case CHIP_HAWAII:

		case CHIP_TOPAZ:

		case CHIP_TONGA:

		case CHIP_FIJI:

		case CHIP_POLARIS10:

		case CHIP_POLARIS11:

		case CHIP_POLARIS12:

		case CHIP_VEGAM:

		case CHIP_VEGA20:

		case CHIP_VEGA10:

		case CHIP_VEGA12:

		case CHIP_RAVEN:

		case CHIP_ARCTURUS:

		case CHIP_RENOIR:

		case CHIP_NAVI10:

		case CHIP_NAVI14:

		case CHIP_NAVI12:

		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_DIMGREY_CAVEFISH:

		case CHIP_BEIGE_GOBY:

		case CHIP_VANGOGH:

		case CHIP_ALDEBARAN:

			break;

		default:

#ifdef CONFIG_DRM_AMDGPU_SI

		case CHIP_VERDE:

		case CHIP_TAHITI:

		case CHIP_PITCAIRN:

		case CHIP_OLAND:

		case CHIP_HAINAN:

#endif

#ifdef CONFIG_DRM_AMDGPU_CIK

		case CHIP_KAVERI:

		case CHIP_KABINI:

		case CHIP_MULLINS:

#endif

		case CHIP_CARRIZO:

		case CHIP_STONEY:

		case CHIP_CYAN_SKILLFISH:

			goto disabled;

		default:

			break;

		}

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+27 −5
Original line number Diff line number Diff line
@@ -243,6 +243,30 @@ static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 
	return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);

}



static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)

{

	/*

	 * So far, apply this quirk only on those Navy Flounder boards which

	 * have a bad harvest table of VCN config.

	 */

	if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&

		(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {

		switch (adev->pdev->revision) {

		case 0xC1:

		case 0xC2:

		case 0xC3:

		case 0xC5:

		case 0xC7:

		case 0xCF:

		case 0xDF:

			adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;

			break;

		default:

			break;

		}

	}

}



static int amdgpu_discovery_init(struct amdgpu_device *adev)

{

	struct table_info *info;
@@ -548,11 +572,9 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 
			break;

		}

	}

	/* some IP discovery tables on Navy Flounder don't have this set correctly */

	if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&

	    (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)) &&

	    (adev->pdev->revision != 0xFF))

		adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;



	amdgpu_discovery_harvest_config_quirk(adev);



	if (vcn_harvest_count == adev->vcn.num_vcn_inst) {

		adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;

		adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+0 −5
Original line number Diff line number Diff line
@@ -1907,11 +1907,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, 
			return -ENODEV;

	}



	if (flags == 0) {

		DRM_INFO("Unsupported asic.  Remove me when IP discovery init is in place.\n");

		return -ENODEV;

	}



	if (amdgpu_virtual_display ||

	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))

		supports_atomic = true;

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+7 −13
Original line number Diff line number Diff line
@@ -625,20 +625,20 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 
	adev->virt.fw_reserve.p_vf2pf = NULL;

	adev->virt.vf2pf_update_interval_ms = 0;



	if (adev->bios != NULL) {

		adev->virt.vf2pf_update_interval_ms = 2000;

	if (adev->mman.fw_vram_usage_va != NULL) {

		/* go through this logic in ip_init and reset to init workqueue*/

		amdgpu_virt_exchange_data(adev);



		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);

		schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));

	} else if (adev->bios != NULL) {

		/* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/

		adev->virt.fw_reserve.p_pf2vf =

			(struct amd_sriov_msg_pf2vf_info_header *)

			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));



		amdgpu_virt_read_pf2vf_data(adev);

	}



	if (adev->virt.vf2pf_update_interval_ms != 0) {

		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);

		schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));

	}

}
@@ -674,12 +674,6 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 
				if (adev->virt.ras_init_done)

					amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);

			}

	} else if (adev->bios != NULL) {

		adev->virt.fw_reserve.p_pf2vf =

			(struct amd_sriov_msg_pf2vf_info_header *)

			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));



		amdgpu_virt_read_pf2vf_data(adev);

	}

}

drivers/gpu/drm/amd/amdgpu/cik.c

+4 −0
Original line number Diff line number Diff line
@@ -1428,6 +1428,10 @@ static int cik_asic_reset(struct amdgpu_device *adev) 
{

	int r;



	/* APUs don't have full asic reset */

	if (adev->flags & AMD_IS_APU)

		return 0;



	if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {

		dev_info(adev->dev, "BACO reset\n");

		r = amdgpu_dpm_baco_reset(adev);