Commit ccdf6f80 authored by Alexander Usyskin's avatar Alexander Usyskin Committed by Greg Kroah-Hartman
Browse files

mei: me: disable driver on the ign firmware 



Add a quirk to disable MEI interface on Intel PCH Ignition (IGN)
as the IGN firmware doesn't support the protocol.

Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20220215080438.264876-1-tomas.winkler@intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2c5d8f7c

drivers/misc/mei/hw-me-regs.h

+1 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ 
#define PCI_CFG_HFS_2         0x48

#define PCI_CFG_HFS_3         0x60

#  define PCI_CFG_HFS_3_FW_SKU_MSK   0x00000070

#  define PCI_CFG_HFS_3_FW_SKU_IGN   0x00000000

#  define PCI_CFG_HFS_3_FW_SKU_SPS   0x00000060

#define PCI_CFG_HFS_4         0x64

#define PCI_CFG_HFS_5         0x68

drivers/misc/mei/hw-me.c

+12 −11
Original line number Diff line number Diff line
@@ -1405,16 +1405,16 @@ static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev) 
	.quirk_probe = mei_me_fw_type_sps_4



/**

 * mei_me_fw_type_sps() - check for sps sku

 * mei_me_fw_type_sps_ign() - check for sps or ign sku

 *

 * Read ME FW Status register to check for SPS Firmware.

 * The SPS FW is only signaled in pci function 0

 * Read ME FW Status register to check for SPS or IGN Firmware.

 * The SPS/IGN FW is only signaled in pci function 0

 *

 * @pdev: pci device

 *

 * Return: true in case of SPS firmware

 * Return: true in case of SPS/IGN firmware

 */

static bool mei_me_fw_type_sps(const struct pci_dev *pdev)

static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev)

{

	u32 reg;

	u32 fw_type;
@@ -1427,14 +1427,15 @@ static bool mei_me_fw_type_sps(const struct pci_dev *pdev) 


	dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);



	return fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;

	return fw_type == PCI_CFG_HFS_3_FW_SKU_IGN ||

	       fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;

}



#define MEI_CFG_KIND_ITOUCH                     \

	.kind = "itouch"



#define MEI_CFG_FW_SPS                          \

	.quirk_probe = mei_me_fw_type_sps

#define MEI_CFG_FW_SPS_IGN                      \

	.quirk_probe = mei_me_fw_type_sps_ign



#define MEI_CFG_FW_VER_SUPP                     \

	.fw_ver_supported = 1
@@ -1535,7 +1536,7 @@ static const struct mei_cfg mei_me_pch12_sps_cfg = { 
	MEI_CFG_PCH8_HFS,

	MEI_CFG_FW_VER_SUPP,

	MEI_CFG_DMA_128,

	MEI_CFG_FW_SPS,

	MEI_CFG_FW_SPS_IGN,

};



/* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion
@@ -1545,7 +1546,7 @@ static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = { 
	MEI_CFG_KIND_ITOUCH,

	MEI_CFG_PCH8_HFS,

	MEI_CFG_FW_VER_SUPP,

	MEI_CFG_FW_SPS,

	MEI_CFG_FW_SPS_IGN,

};



/* Tiger Lake and newer devices */
@@ -1562,7 +1563,7 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = { 
	MEI_CFG_FW_VER_SUPP,

	MEI_CFG_DMA_128,

	MEI_CFG_TRC,

	MEI_CFG_FW_SPS,

	MEI_CFG_FW_SPS_IGN,

};



/*