Commit ccd1c07f authored by Tong Tiangen's avatar Tong Tiangen
Browse files

arm64: kernel: disable CNP on LINXICORE9100 

hulk inclusion
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/I7F28R


CVE: NA

--------------------------------

On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when
TTBRx.CNP=1 differs from the standard ARM core. This causes issues when tlb
entries sharing between CPU cores. Avoid these issues by disabling CNP
feature for Hisilicon LINXICORE9100 cores.

Signed-off-by: default avatarTong Tiangen <tongtiangen@huawei.com>
parent 9d6f05f7

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -149,6 +149,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | TSV{110,200}    | #1980005        | HISILICON_ERRATUM_1980005   |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -802,6 +802,17 @@ config HISILICON_ERRATUM_1980005 


	  If unsure, say N.



config HISILICON_ERRATUM_162100125

	bool "Hisilicon erratum 162100125"

	default y

	help

	  On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when

	  TTBRx.CNP=1 differs from the standard ARM core. This causes issues when

	  tlb entries sharing between CPU cores. Avoid these issues by disabling

	  CNP support for Hisilicon LINXICORE9100 cores.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -390,6 +390,7 @@ CONFIG_QCOM_FALKOR_ERRATUM_E1041=y 
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y

CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y

# CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set

CONFIG_HISILICON_ERRATUM_162100125=y

# end of ARM errata workarounds via the alternatives framework



CONFIG_ARM64_4K_PAGES=y

arch/arm64/include/asm/cpucaps.h

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ 
#define ARM64_SPECTRE_BHB			66

#define ARM64_WORKAROUND_1742098	67

#define ARM64_HAS_WFXT				68

#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125	69



#define ARM64_NCAPS				80

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ 


#define HISI_CPU_PART_TSV110		0xD01

#define HISI_CPU_PART_TSV200		0xD02

#define HISI_CPU_PART_LINXICORE9100	0xD02



#define PHYTIUM_CPU_PART_1500A		0X660

#define PHYTIUM_CPU_PART_2000AHK	0X661
@@ -161,6 +162,7 @@ 
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_TSV200 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV200)

#define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100)

#define MIDR_FT_1500A    MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_1500A)

#define MIDR_FT_2000AHK	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000AHK)

#define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)