Commit ccbbfe06 authored by Avihai Horon's avatar Avihai Horon Committed by Leon Romanovsky
Browse files

net/mlx5: Update relaxed ordering read HCA capabilities 



Rename existing HCA capability relaxed_ordering_read to
relaxed_ordering_read_pci_enabled. This is in accordance with recent PRM
change to better describe the capability, as it's set only if both the
device supports relaxed ordering (RO) read and RO is enabled in PCI
config space.

In addition, add new HCA capability relaxed_ordering_read which is set
if the device supports RO read, regardless of RO in PCI config space.
This will be used in the following patch to allow RO in VFs and VMs.

Signed-off-by: default avatarAvihai Horon <avihaih@nvidia.com>
Reviewed-by: default avatarShay Drory <shayd@nvidia.com>
Link: https://lore.kernel.org/r/caa0002fd8135086357dfcc368e2f5cc73b08480.1681131553.git.leon@kernel.org


Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent d43b020b

drivers/infiniband/hw/mlx5/mr.c

+3 −2
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr, 
	if (acc & IB_ACCESS_RELAXED_ORDERING) {

		if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))

			MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);

		if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&

		if (MLX5_CAP_GEN(dev->mdev,

				 relaxed_ordering_read_pci_enabled) &&

		    pcie_relaxed_ordering_enabled(dev->mdev->pdev))

			MLX5_SET(mkc, mkc, relaxed_ordering_read, 1);

	}
@@ -791,7 +792,7 @@ static int get_unchangeable_access_flags(struct mlx5_ib_dev *dev, 
		ret |= IB_ACCESS_RELAXED_ORDERING;



	if ((access_flags & IB_ACCESS_RELAXED_ORDERING) &&

	    MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&

	    MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled) &&

	    !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))

		ret |= IB_ACCESS_RELAXED_ORDERING;

drivers/infiniband/hw/mlx5/umr.h

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev, 
		return false;



	if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&

	    MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&

	    MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled) &&

	    !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))

		return false;

drivers/net/ethernet/mellanox/mlx5/core/en_common.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 
{

	bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev);

	bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);

	bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);

	bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled);



	MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);

	MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write);

include/linux/mlx5/mlx5_ifc.h

+3 −2
Original line number Diff line number Diff line
@@ -1511,7 +1511,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { 


	u8         log_max_eq_sz[0x8];

	u8         relaxed_ordering_write[0x1];

	u8         relaxed_ordering_read[0x1];

	u8         relaxed_ordering_read_pci_enabled[0x1];

	u8         log_max_mkey[0x6];

	u8         reserved_at_f0[0x6];

	u8	   terminate_scatter_list_mkey[0x1];
@@ -1727,7 +1727,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 


	u8         reserved_at_320[0x3];

	u8         log_max_transport_domain[0x5];

	u8         reserved_at_328[0x3];

	u8         reserved_at_328[0x2];

	u8	   relaxed_ordering_read[0x1];

	u8         log_max_pd[0x5];

	u8         reserved_at_330[0x9];

	u8         q_counter_aggregation[0x1];