Commit cca85283 authored by Raju Rangoju's avatar Raju Rangoju Committed by David S. Miller
Browse files

cxgb4: add error handlers to LE intr_handler 



cxgb4 does not look for HASHTBLMEMCRCERR and CMDTIDERR
bits in LE_DB_INT_CAUSE register, but these are enabled
in LE_DB_INT_ENABLE. So, add error handlers to LE
interrupt handler to emit a warning or alert message
for hash table mem crc and cmd tid errors

Signed-off-by: default avatarRaju Rangoju <rajur@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4718a471

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+2 −0
Original line number Diff line number Diff line
@@ -4745,9 +4745,11 @@ static void le_intr_handler(struct adapter *adap) 
	static struct intr_info t6_le_intr_info[] = {

		{ T6_LIPMISS_F, "LE LIP miss", -1, 0 },

		{ T6_LIP0_F, "LE 0 LIP error", -1, 0 },

		{ CMDTIDERR_F, "LE cmd tid error", -1, 1 },

		{ TCAMINTPERR_F, "LE parity error", -1, 1 },

		{ T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },

		{ SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },

		{ HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },

		{ 0 }

	};

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+8 −0
Original line number Diff line number Diff line
@@ -3017,6 +3017,14 @@ 
#define REV_V(x) ((x) << REV_S)

#define REV_G(x) (((x) >> REV_S) & REV_M)



#define HASHTBLMEMCRCERR_S    27

#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)

#define HASHTBLMEMCRCERR_F    HASHTBLMEMCRCERR_V(1U)



#define CMDTIDERR_S    22

#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)

#define CMDTIDERR_F    CMDTIDERR_V(1U)



#define T6_UNKNOWNCMD_S    3

#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)

#define T6_UNKNOWNCMD_F    T6_UNKNOWNCMD_V(1U)