Commit cc85345d authored by Umesh Nerlige Ramappa's avatar Umesh Nerlige Ramappa Committed by John Harrison
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drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers 



User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.

Signed-off-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-10-umesh.nerlige.ramappa@intel.com
parent 2db609c0

drivers/gpu/drm/i915/i915_perf.c

+19 −2
Original line number Diff line number Diff line
@@ -1754,6 +1754,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream *stream) 
static int alloc_oa_buffer(struct i915_perf_stream *stream)

{

	struct drm_i915_private *i915 = stream->perf->i915;

	struct intel_gt *gt = stream->engine->gt;

	struct drm_i915_gem_object *bo;

	struct i915_vma *vma;

	int ret;
@@ -1773,11 +1774,22 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream) 
	i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);



	/* PreHSW required 512K alignment, HSW requires 16M */

	vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);

	vma = i915_vma_instance(bo, &gt->ggtt->vm, NULL);

	if (IS_ERR(vma)) {

		ret = PTR_ERR(vma);

		goto err_unref;

	}



	/*

	 * PreHSW required 512K alignment.

	 * HSW and onwards, align to requested size of OA buffer.

	 */

	ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);

	if (ret) {

		drm_err(&gt->i915->drm, "Failed to pin OA buffer %d\n", ret);

		goto err_unref;

	}



	stream->oa_buffer.vma = vma;



	stream->oa_buffer.vaddr =
@@ -1827,6 +1839,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs, 
static int alloc_noa_wait(struct i915_perf_stream *stream)

{

	struct drm_i915_private *i915 = stream->perf->i915;

	struct intel_gt *gt = stream->engine->gt;

	struct drm_i915_gem_object *bo;

	struct i915_vma *vma;

	const u64 delay_ticks = 0xffffffffffffffff -
@@ -1867,12 +1880,16 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) 
	 * multiple OA config BOs will have a jump to this address and it

	 * needs to be fixed during the lifetime of the i915/perf stream.

	 */

	vma = i915_gem_object_ggtt_pin_ww(bo, &ww, NULL, 0, 0, PIN_HIGH);

	vma = i915_vma_instance(bo, &gt->ggtt->vm, NULL);

	if (IS_ERR(vma)) {

		ret = PTR_ERR(vma);

		goto out_ww;

	}



	ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);

	if (ret)

		goto out_ww;



	batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);

	if (IS_ERR(batch)) {

		ret = PTR_ERR(batch);