Commit cc828c1b authored by Hao Lan's avatar Hao Lan Committed by Jiantao Xiao
Browse files

net: hns3: add new 200G link modes for hisilicon device 

mainline inclusion
from mainline-v6.9-rc1
commit dd1f65f0db27467f742d8c6e5276b8e8e0c83890
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I98TUP
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dd1f65f0db27467f742d8c6e5276b8e8e0c83890



----------------------------------------------------------------------

The hisilicon device now supports a new 200G link interface,
which query from firmware in a new bit. Therefore,
the HCLGE_SUPPORT_200G_R4_BIT capability bit has been added.
The HCLGE_SUPPORT_200G_BIT has been renamed as
HCLGE_SUPPORT_200G_R4_EXT_BIT, and the firmware has
extended support for this mode.

Fixes: ae6f010c ("net: hns3: add support for 200G device")
Signed-off-by: default avatarHao Lan <lanhao@huawei.com>
Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 60372139

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+18 −10
Original line number Diff line number Diff line
@@ -885,7 +885,7 @@ static const struct hclge_speed_bit_map speed_bit_map[] = { 
	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},

	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},

	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},

	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},

	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS},

};



static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
@@ -941,7 +941,7 @@ static void hclge_update_fec_support(struct hclge_mac *mac) 
				 mac->supported);

}



static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = {

static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
@@ -949,10 +949,12 @@ static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = {

static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},
@@ -960,11 +962,13 @@ static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = { 
	 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT,

	 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT,

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT,

	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = {

static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
@@ -972,10 +976,12 @@ static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = {

static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
@@ -984,7 +990,9 @@ static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

};



static void hclge_convert_setting_sr(u16 speed_ability,
@@ -1155,7 +1163,7 @@ static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 


static u32 hclge_get_max_speed(u16 speed_ability)

{

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

	if (speed_ability & HCLGE_SUPPORT_200G_BITS)

		return HCLGE_MAC_SPEED_200G;



	if (speed_ability & HCLGE_SUPPORT_100G_BITS)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+4 −1
Original line number Diff line number Diff line
@@ -193,9 +193,10 @@ enum HLCGE_PORT_TYPE { 
#define HCLGE_SUPPORT_40G_BIT		BIT(5)

#define HCLGE_SUPPORT_100M_BIT		BIT(6)

#define HCLGE_SUPPORT_10M_BIT		BIT(7)

#define HCLGE_SUPPORT_200G_BIT		BIT(8)

#define HCLGE_SUPPORT_200G_R4_EXT_BIT	BIT(8)

#define HCLGE_SUPPORT_50G_R1_BIT	BIT(9)

#define HCLGE_SUPPORT_100G_R2_BIT	BIT(10)

#define HCLGE_SUPPORT_200G_R4_BIT	BIT(11)



#define HCLGE_SUPPORT_GE \

	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
@@ -203,6 +204,8 @@ enum HLCGE_PORT_TYPE { 
	(HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT)

#define HCLGE_SUPPORT_100G_BITS \

	(HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT)

#define HCLGE_SUPPORT_200G_BITS \

	(HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT)



enum HCLGE_DEV_STATE {

	HCLGE_STATE_REINITING,