Commit cc69fc48 authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge branches 'arm/msm', 'arm/allwinner', 'arm/smmu', 'x86/vt-d', 'hyper-v',... 

Merge branches 'arm/msm', 'arm/allwinner', 'arm/smmu', 'x86/vt-d', 'hyper-v', 'core' and 'x86/amd' into next
parents 3d77e6a8 c4e0f3b2 79074f61 0299a1a8 71974cfb 9f510d1e edcc40d2 736c3333

Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner H6 IOMMU Device Tree Bindings



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <mripard@kernel.org>



properties:

  "#iommu-cells":

    const: 1

    description:

      The content of the cell is the master ID.



  compatible:

    const: allwinner,sun50i-h6-iommu



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



required:

  - "#iommu-cells"

  - compatible

  - reg

  - interrupts

  - clocks

  - resets



additionalProperties: false



examples:

  - |

      #include <dt-bindings/interrupt-controller/arm-gic.h>

      #include <dt-bindings/interrupt-controller/irq.h>



      #include <dt-bindings/clock/sun50i-h6-ccu.h>

      #include <dt-bindings/reset/sun50i-h6-ccu.h>



      iommu: iommu@30f0000 {

          compatible = "allwinner,sun50i-h6-iommu";

          reg = <0x030f0000 0x10000>;

          interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

          clocks = <&ccu CLK_BUS_IOMMU>;

          resets = <&ccu RST_BUS_IOMMU>;

          #iommu-cells = <1>;

      };



...

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

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@@ -41,7 +41,9 @@ properties: 
          - const: arm,mmu-500

          - const: arm,smmu-v2

      - items:

          - const: arm,mmu-401

          - enum:

              - arm,mmu-400

              - arm,mmu-401

          - const: arm,smmu-v1

      - enum:

          - arm,smmu-v1

Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt

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@@ -184,6 +184,9 @@ For the compatible strings below the following phandle references are required: 
		    followed by the offset within syscon for conn_box_spare0

		    register.



The Hexagon node must contain iommus property as described in ../iommu/iommu.txt

on platforms which do not have TrustZone.



= SUBNODES:

The Hexagon node must contain two subnodes, named "mba" and "mpss" representing

the memory regions used by the Hexagon firmware. Each sub-node must contain:

arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi

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@@ -631,6 +631,11 @@ ap_ts_i2c: &i2c14 { 
	status = "okay";

};



&mss_pil {

	iommus = <&apps_smmu 0x780 0x1>,

		 <&apps_smmu 0x724 0x3>;

};



&pm8998_pwrkey {

	status = "disabled";

};

drivers/iommu/Kconfig

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@@ -303,6 +303,15 @@ config ROCKCHIP_IOMMU 
	  Say Y here if you are using a Rockchip SoC that includes an IOMMU

	  device.



config SUN50I_IOMMU

	bool "Allwinner H6 IOMMU Support"

	depends on ARCH_SUNXI || COMPILE_TEST

	select ARM_DMA_USE_IOMMU

	select IOMMU_API

	select IOMMU_DMA

	help

	  Support for the IOMMU introduced in the Allwinner H6 SoCs.



config TEGRA_IOMMU_GART

	bool "Tegra GART IOMMU Support"

	depends on ARCH_TEGRA_2x_SOC