Commit cc4f9dcd authored by Yong Wu's avatar Yong Wu Committed by Krzysztof Kozlowski
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memory: mtk-smi: mt8195: Add smi support 



MT8195 has two smi-common, their IP are the same. Only the larbs that
connect with the smi-common are different. thus the bus_sel are different
for the two smi-common.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Link: https://lore.kernel.org/r/20210914113703.31466-11-yong.wu@mediatek.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
parent 912fea8b

drivers/memory/mtk-smi.c

+26 −0
Original line number Diff line number Diff line
@@ -261,6 +261,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 
	.config_port                = mtk_smi_larb_config_port_gen2_general,

};



static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {

	.config_port                = mtk_smi_larb_config_port_gen2_general,

};



static const struct of_device_id mtk_smi_larb_of_ids[] = {

	{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},

	{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
@@ -269,6 +273,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { 
	{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},

	{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},

	{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},

	{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},

	{}

};
@@ -443,6 +448,24 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 
		    F_MMU1_LARB(6),

};



static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {

	.type     = MTK_SMI_GEN2,

	.has_gals = true,

	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |

		    F_MMU1_LARB(7),

};



static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {

	.type     = MTK_SMI_GEN2,

	.has_gals = true,

	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),

};



static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {

	.type     = MTK_SMI_GEN2_SUB_COMM,

	.has_gals = true,

};



static const struct of_device_id mtk_smi_common_of_ids[] = {

	{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},

	{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
@@ -451,6 +474,9 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { 
	{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},

	{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},

	{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},

	{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},

	{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},

	{.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},

	{}

};