Commit cc4c26d4 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Generated register update 



Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5

Small bit of .c churn in the phy code to adapt to split up of phy
related registers.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent b3fbfa23

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+42 −18
Original line number Diff line number Diff line
@@ -8,21 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)



Copyright (C) 2013-2020 by the following authors:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)



Copyright (C) 2013-2021 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 


#define REG_A2XX_NQWAIT_UNTIL					0x00000394



#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT			0x00000395

#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT			0x00000395



#define REG_A2XX_RBBM_PERFCOUNTER1_LO				0x00000397

#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT			0x00000396



#define REG_A2XX_RBBM_PERFCOUNTER1_HI				0x00000398

#define REG_A2XX_RBBM_PERFCOUNTER0_LO				0x00000397



#define REG_A2XX_RBBM_PERFCOUNTER0_HI				0x00000398



#define REG_A2XX_RBBM_PERFCOUNTER1_LO				0x00000399



#define REG_A2XX_RBBM_PERFCOUNTER1_HI				0x0000039a



#define REG_A2XX_RBBM_DEBUG					0x0000039b
@@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 


#define REG_A2XX_RB_PERFCOUNTER0_SELECT				0x00000f04



#define REG_A2XX_RB_PERFCOUNTER1_SELECT				0x00000f05



#define REG_A2XX_RB_PERFCOUNTER2_SELECT				0x00000f06



#define REG_A2XX_RB_PERFCOUNTER3_SELECT				0x00000f07



#define REG_A2XX_RB_PERFCOUNTER0_LOW				0x00000f08



#define REG_A2XX_RB_PERFCOUNTER0_HI				0x00000f09



#define REG_A2XX_RB_PERFCOUNTER1_LOW				0x00000f0a



#define REG_A2XX_RB_PERFCOUNTER1_HI				0x00000f0b



#define REG_A2XX_RB_PERFCOUNTER2_LOW				0x00000f0c



#define REG_A2XX_RB_PERFCOUNTER2_HI				0x00000f0d



#define REG_A2XX_RB_PERFCOUNTER3_LOW				0x00000f0e



#define REG_A2XX_RB_PERFCOUNTER3_HI				0x00000f0f



#define REG_A2XX_SQ_TEX_0					0x00000000

#define A2XX_SQ_TEX_0_TYPE__MASK				0x00000003

#define A2XX_SQ_TEX_0_TYPE__SHIFT				0

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+20 −20
Original line number Diff line number Diff line
@@ -8,21 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)



Copyright (C) 2013-2020 by the following authors:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)



Copyright (C) 2013-2021 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 
#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT				16

static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;

}



static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
@@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT				16

static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;

}



#define REG_A3XX_RB_BLEND_GREEN					0x000020e5
@@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT			16

static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;

}



#define REG_A3XX_RB_BLEND_BLUE					0x000020e6
@@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT				16

static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;

}



#define REG_A3XX_RB_BLEND_ALPHA					0x000020e7
@@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16

static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;

}



#define REG_A3XX_RB_CLEAR_COLOR_DW0				0x000020e8

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+19 −19
Original line number Diff line number Diff line
@@ -8,21 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)



Copyright (C) 2013-2020 by the following authors:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)



Copyright (C) 2013-2021 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) 
#define A4XX_RB_BLEND_RED_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;

}



#define REG_A4XX_RB_BLEND_RED_F32				0x000020f1
@@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) 
#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;

}



#define REG_A4XX_RB_BLEND_GREEN_F32				0x000020f3
@@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) 
#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;

}



#define REG_A4XX_RB_BLEND_BLUE_F32				0x000020f5
@@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) 
#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;

}



#define REG_A4XX_RB_BLEND_ALPHA_F32				0x000020f7

drivers/gpu/drm/msm/adreno/a5xx.xml.h

+70 −25
Original line number Diff line number Diff line
@@ -8,21 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)

- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)



Copyright (C) 2013-2020 by the following authors:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)



Copyright (C) 2013-2021 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -2021,6 +2021,7 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) 
#define A5XX_RBBM_STATUS_HI_BUSY				0x00000001



#define REG_A5XX_RBBM_STATUS3					0x00000530

#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000



#define REG_A5XX_RBBM_INT_0_STATUS				0x000004e1
@@ -2351,6 +2352,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7				0x00000e57



#define REG_A5XX_VPC_DBG_ECO_CNTL				0x00000e60

#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS			0x00000400



#define REG_A5XX_VPC_ADDR_MODE_CNTL				0x00000e61
@@ -2808,7 +2810,19 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 
#define REG_A5XX_GRAS_CL_CNTL					0x0000e000

#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040



#define REG_A5XX_UNKNOWN_E001					0x0000e001

#define REG_A5XX_GRAS_VS_CL_CNTL				0x0000e001

#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff

#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0

static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)

{

	return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;

}

#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00

#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT			8

static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)

{

	return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;

}



#define REG_A5XX_UNKNOWN_E004					0x0000e004
@@ -3345,7 +3359,7 @@ static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) 
#define A5XX_RB_BLEND_RED_FLOAT__SHIFT				16

static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;

}



#define REG_A5XX_RB_BLEND_RED_F32				0x0000e1a1
@@ -3373,7 +3387,7 @@ static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) 
#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT			16

static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;

}



#define REG_A5XX_RB_BLEND_GREEN_F32				0x0000e1a3
@@ -3401,7 +3415,7 @@ static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) 
#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT				16

static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;

}



#define REG_A5XX_RB_BLEND_BLUE_F32				0x0000e1a5
@@ -3429,7 +3443,7 @@ static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) 
#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16

static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)

{

	return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;

	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;

}



#define REG_A5XX_RB_BLEND_ALPHA_F32				0x0000e1a7
@@ -3806,7 +3820,25 @@ static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 


#define REG_A5XX_VPC_GS_SIV_CNTL				0x0000e298



#define REG_A5XX_UNKNOWN_E29A					0x0000e29a

#define REG_A5XX_VPC_CLIP_CNTL					0x0000e29a

#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff

#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT			0

static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)

{

	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;

}

#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00

#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8

static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)

{

	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;

}

#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000

#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16

static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)

{

	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;

}



#define REG_A5XX_VPC_PACK					0x0000e29d

#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK			0x000000ff
@@ -3910,7 +3942,13 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su 
}

#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE			0x00000040



#define REG_A5XX_UNKNOWN_E389					0x0000e389

#define REG_A5XX_PC_CLIP_CNTL					0x0000e389

#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff

#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT			0

static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)

{

	return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;

}



#define REG_A5XX_PC_RESTART_INDEX				0x0000e38c
@@ -4302,7 +4340,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 
#define REG_A5XX_SP_FS_OBJ_START_HI				0x0000e5c4



#define REG_A5XX_SP_BLEND_CNTL					0x0000e5c9

#define A5XX_SP_BLEND_CNTL_ENABLED				0x00000001

#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff

#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0

static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)

{

	return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;

}

#define A5XX_SP_BLEND_CNTL_UNK8					0x00000100

#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
@@ -5192,8 +5235,8 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) 
}



#define REG_A5XX_TEX_SAMP_2					0x00000002

#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xfffffff0

#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			4

#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80

#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			7

static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)

{

	return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
@@ -5273,6 +5316,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) 
}



#define REG_A5XX_TEX_CONST_2					0x00000002

#define A5XX_TEX_CONST_2_UNK4					0x00000010

#define A5XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f

#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT			0

static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
@@ -5291,6 +5335,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) 
{

	return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;

}

#define A5XX_TEX_CONST_2_UNK31					0x80000000



#define REG_A5XX_TEX_CONST_3					0x00000003

#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff

drivers/gpu/drm/msm/adreno/a6xx.xml.h

+1059 −1142

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