Commit cc3c470a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM driver updates from Arnd Bergmann:
 "There are minor updates to SoC specific drivers for chips by Rockchip,
  Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.

  Noteworthy driver changes include:

   - Several conversions of DT bindings to yaml format.

   - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.

   - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
     and support for more chips in the RPMh power domains and the
     soc-id.

   - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.

   - Apple M1 gains support for the on-chip NVMe controller, making it
     possible to finally use the internal disks. This also includes SoC
     drivers for their RTKit IPC and for the SART DMA address filter.

  For other subsystems that merge their drivers through the SoC tree, we
  have

   - Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
     SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
     now has a cache for firmware argument structures as an
     optimization, and SCMI now supports the 3.1 version of the
     specification.

   - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
     drivers

   - Memory controller updates for Tegra, and a few updates for other
     platforms"

* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
  memory: tegra: Add MC error logging on Tegra186 onward
  memory: tegra: Add memory controller channels support
  memory: tegra: Add APE memory clients for Tegra234
  memory: tegra: Add Tegra234 support
  nvme-apple: fix sparse endianess warnings
  soc/tegra: pmc: Document core domain fields
  soc: qcom: pdr: use static for servreg_* variables
  soc: imx: fix semicolon.cocci warnings
  soc: renesas: R-Car V3U is R-Car Gen4
  soc: imx: add i.MX8MP HDMI blk-ctrl
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  soc: imx: add i.MX8MP HSIO blk-ctrl
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: qcom: llcc: Add sc8180x and sc8280xp configurations
  dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
  soc/tegra: pmc: Select REGMAP
  dt-bindings: reset: st,sti-powerdown: Convert to yaml
  dt-bindings: reset: st,sti-picophyreset: Convert to yaml
  dt-bindings: reset: socfpga: Convert to yaml
  dt-bindings: reset: snps,axs10x-reset: Convert to yaml
  ...
parents ae862183 d4a3b442

Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ properties: 
    enum:

      - qcom,sc7180-llcc

      - qcom,sc7280-llcc

      - qcom,sc8180x-llcc

      - qcom,sc8280xp-llcc

      - qcom,sdm845-llcc

      - qcom,sm6350-llcc

      - qcom,sm8150-llcc

Documentation/devicetree/bindings/arm/qcom.yaml

+20 −0
Original line number Diff line number Diff line
@@ -39,8 +39,11 @@ description: | 
        msm8994

        msm8996

        sa8155p

        sa8540p

        sc7180

        sc7280

        sc8180x

        sc8280xp

        sdm630

        sdm632

        sdm660
@@ -226,6 +229,18 @@ properties: 
              - google,senor

          - const: qcom,sc7280



      - items:

          - enum:

              - lenovo,flex-5g

              - microsoft,surface-prox

              - qcom,sc8180x-primus

          - const: qcom,sc8180x



      - items:

          - enum:

              - qcom,sc8280xp-qrd

          - const: qcom,sc8280xp



      - items:

          - enum:

              - fairphone,fp3
@@ -259,6 +274,11 @@ properties: 
              - qcom,sa8155p-adp

          - const: qcom,sa8155p



      - items:

          - enum:

              - qcom,sa8295p-adp

          - const: qcom,sa8540p



      - items:

          - enum:

              - fairphone,fp4

Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml

0 → 100644
+147 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs



maintainers:

  - Michael Srba <Michael.Srba@seznam.cz>



description: |

  This binding describes the dependencies (clocks, resets, power domains) which

  need to be turned on in a sequence before communication over the AHB bus

  becomes possible.



  Additionally, the reg property is used to pass to the driver the location of

  two sadly undocumented registers which need to be poked as part of the sequence.



  The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart

  controllers, a hexagon core, and a clock controller which provides clocks for

  the above.



properties:

  compatible:

    items:

      - const: qcom,msm8998-ssc-block-bus

      - const: qcom,ssc-block-bus



  reg:

    description: |

      Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1

      registers

    minItems: 2

    maxItems: 2



  reg-names:

    items:

      - const: mpm_sscaon_config0

      - const: mpm_sscaon_config1



  '#address-cells':

    enum: [ 1, 2 ]



  '#size-cells':

    enum: [ 1, 2 ]



  ranges: true



  clocks:

    minItems: 6

    maxItems: 6



  clock-names:

    items:

      - const: xo

      - const: aggre2

      - const: gcc_im_sleep

      - const: aggre2_north

      - const: ssc_xo

      - const: ssc_ahbs



  power-domains:

    description: Power domain phandles for the ssc_cx and ssc_mx power domains

    minItems: 2

    maxItems: 2



  power-domain-names:

    items:

      - const: ssc_cx

      - const: ssc_mx



  resets:

    description: |

      Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the

      branch control register associated with the ssc_xo and ssc_ahbs clocks)

    minItems: 2

    maxItems: 2



  reset-names:

    items:

      - const: ssc_reset

      - const: ssc_bcr



  qcom,halt-regs:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: describes how to locate the ssc AXI halt register

    items:

      - items:

          - description: Phandle reference to a syscon representing TCSR

          - description: offset for the ssc AXI halt register



required:

  - compatible

  - reg

  - reg-names

  - '#address-cells'

  - '#size-cells'

  - ranges

  - clocks

  - clock-names

  - power-domains

  - power-domain-names

  - resets

  - reset-names

  - qcom,halt-regs



additionalProperties:

  type: object



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-msm8998.h>

    #include <dt-bindings/clock/qcom,rpmcc.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    soc {

        #address-cells = <1>;

        #size-cells = <1>;



        // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;

        ssc_ahb_slave: bus@10ac008 {

            #address-cells = <1>;

            #size-cells = <1>;

            ranges;



            compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";

            reg = <0x10ac008 0x4>, <0x10ac010 0x4>;

            reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";



            clocks = <&xo>,

                     <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,

                     <&gcc GCC_IM_SLEEP>,

                     <&gcc AGGRE2_SNOC_NORTH_AXI>,

                     <&gcc SSC_XO>,

                     <&gcc SSC_CNOC_AHBS_CLK>;

            clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";



            resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;

            reset-names = "ssc_reset", "ssc_bcr";



            power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;

            power-domain-names = "ssc_cx", "ssc_mx";



            qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;

        };

    };

Documentation/devicetree/bindings/firmware/qcom,scm.txt

+2 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ Required properties: 
 * "qcom,scm-msm8953"

 * "qcom,scm-msm8960"

 * "qcom,scm-msm8974"

 * "qcom,scm-msm8976"

 * "qcom,scm-msm8994"

 * "qcom,scm-msm8996"

 * "qcom,scm-msm8998"
@@ -37,7 +38,7 @@ Required properties: 
 * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and

   "qcom,scm-msm8960"

 * core, iface and bus clocks required for "qcom,scm-apq8084",

   "qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974"

   "qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976"

- clock-names: Must contain "core" for the core clock, "iface" for the interface

  clock and "bus" for the bus clock per the requirements of the compatible.

- qcom,dload-mode: phandle to the TCSR hardware block and offset of the

Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml

+4 −4
Original line number Diff line number Diff line
@@ -45,20 +45,20 @@ additionalProperties: false 


examples:

  # Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node

  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt

  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml

  - |



    apps_bcm_voter: bcm_voter {

    apps_bcm_voter: bcm-voter {

        compatible = "qcom,bcm-voter";

    };



  # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node

  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt

  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml

  - |



    #include <dt-bindings/interconnect/qcom,icc.h>



    disp_bcm_voter: bcm_voter {

    disp_bcm_voter: bcm-voter {

        compatible = "qcom,bcm-voter";

        qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;

    };