Commit cc3c44c9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "About the usual for this stage, bunch of amdgpu, a few i915 and a
  scattering of fixes across the board"

  dsc:
   - macro fixes

  simplefb:
   - fix VESA format

  scheduler:
   - timeout handling fix

  fbdev:
   - avoid potential out-of-bounds access in generic fbdev emulation

  ast:
   - improve AST2500+ compat on ARM

  mipi-dsi:
   - small mipi-dsi fix

  amdgpu:
   - VCN3 fixes
   - APUs always support PCI atomics
   - legacy power management fixes
   - DCN 3.1.4 fix
   - DCFCLK fix
   - fix several RAS irq refcount mismatches
   - GPU Reset fix
   - GFX 11.0.4 fix

  i915:
   - taint kernel when force_probe is used
   - NULL deref and div-by-zero fixes for display
   - GuC error capture fix for Xe devices"

* tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amdgpu: change gfx 11.0.4 external_id range
  drm/amdgpu/jpeg: Remove harvest checking for JPEG3
  drm/amdgpu/gfx: disable gfx9 cp_ecc_error_irq only when enabling legacy gfx ras
  drm/amd/pm: avoid potential UBSAN issue on legacy asics
  drm/i915: taint kernel when force probing unsupported devices
  drm/i915/dp: prevent potential div-by-zero
  drm/i915: Fix NULL ptr deref by checking new_crtc_state
  drm/i915/guc: Don't capture Gen8 regs on Xe devices
  drm/amdgpu: disable sdma ecc irq only when sdma RAS is enabled in suspend
  drm/amdgpu: Fix vram recover doesn't work after whole GPU reset (v2)
  drm/amdgpu: drop gfx_v11_0_cp_ecc_error_irq_funcs
  drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
  drm/amd/display: Add symclk workaround during disable link output
  drm/amd/pm: parse pp_handle under appropriate conditions
  drm/amdgpu: set gfx9 onwards APU atomics support to be true
  drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution
  drm/sched: Check scheduler work queue before calling timeout handling
  drm/mipi-dsi: Set the fwnode for mipi_dsi_device
  drm/nouveau/disp: More DP_RECEIVER_CAP_SIZE array fixes
  drm/dsc: fix DP_DSC_MAX_BPP_DELTA_* macro values
  ...
parents 849a4f09 d8843eeb

drivers/firmware/sysfb_simplefb.c

+3 −1
Original line number Diff line number Diff line
@@ -51,7 +51,8 @@ __init bool sysfb_parse_mode(const struct screen_info *si, 
	 *

	 * It's not easily possible to fix this in struct screen_info,

	 * as this could break UAPI. The best solution is to compute

	 * bits_per_pixel here and ignore lfb_depth. In the loop below,

	 * bits_per_pixel from the color bits, reserved bits and

	 * reported lfb_depth, whichever is highest.  In the loop below,

	 * ignore simplefb formats with alpha bits, as EFI and VESA

	 * don't specify alpha channels.

	 */
@@ -60,6 +61,7 @@ __init bool sysfb_parse_mode(const struct screen_info *si, 
					  si->green_size + si->green_pos,

					  si->blue_size + si->blue_pos),

				     si->rsvd_size + si->rsvd_pos);

		bits_per_pixel = max_t(u32, bits_per_pixel, si->lfb_depth);

	} else {

		bits_per_pixel = si->lfb_depth;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+11 −1
Original line number Diff line number Diff line
@@ -3757,6 +3757,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
		adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)

			adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==

			(PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);

	/* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a

	 * internal path natively support atomics, set have_atomics_support to true.

	 */

	else if ((adev->flags & AMD_IS_APU) &&

		(adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)))

		adev->have_atomics_support = true;

	else

		adev->have_atomics_support =

			!pci_enable_atomic_ops_to_root(adev->pdev,
@@ -4506,7 +4512,11 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) 
	dev_info(adev->dev, "recover vram bo from shadow start\n");

	mutex_lock(&adev->shadow_list_lock);

	list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {

		shadow = &vmbo->bo;

		/* If vm is compute context or adev is APU, shadow will be NULL */

		if (!vmbo->shadow)

			continue;

		shadow = vmbo->shadow;



		/* No need to recover an evicted BO */

		if (shadow->tbo.resource->mem_type != TTM_PL_TT ||

		    shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+5 −3
Original line number Diff line number Diff line
@@ -687,9 +687,11 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r 
		if (r)

			return r;



		if (adev->gfx.cp_ecc_error_irq.funcs) {

			r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);

			if (r)

				goto late_fini;

		}

	} else {

		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);

	}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+0 −46
Original line number Diff line number Diff line
@@ -1315,13 +1315,6 @@ static int gfx_v11_0_sw_init(void *handle) 
	if (r)

		return r;



	/* ECC error */

	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,

				  GFX_11_0_0__SRCID__CP_ECC_ERROR,

				  &adev->gfx.cp_ecc_error_irq);

	if (r)

		return r;



	/* FED error */

	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,

				  GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
@@ -4444,7 +4437,6 @@ static int gfx_v11_0_hw_fini(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int r;



	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
@@ -5897,36 +5889,6 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev 
	}

}



#define CP_ME1_PIPE_INST_ADDR_INTERVAL  0x1

#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \

	do { \

		uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \

		tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \

		WREG32_SOC15_IP(GC, reg_addr, tmp); \

	} while (0)



static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,

							struct amdgpu_irq_src *source,

							unsigned type,

							enum amdgpu_interrupt_state state)

{

	uint32_t ecc_irq_state = 0;

	uint32_t pipe0_int_cntl_addr = 0;

	int i = 0;



	ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;



	pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);



	WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);



	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)

		SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,

					ecc_irq_state);



	return 0;

}



static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,

					    struct amdgpu_irq_src *src,

					    unsigned type,
@@ -6341,11 +6303,6 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 
	.process = gfx_v11_0_priv_inst_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {

	.set = gfx_v11_0_set_cp_ecc_error_state,

	.process = amdgpu_gfx_cp_ecc_error_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {

	.process = gfx_v11_0_rlc_gc_fed_irq,

};
@@ -6361,9 +6318,6 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 
	adev->gfx.priv_inst_irq.num_types = 1;

	adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;



	adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */

	adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;



	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */

	adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -3764,6 +3764,7 @@ static int gfx_v9_0_hw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))

		amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);