Commit cc0c986a authored by Dnyaneshwar Bhadane's avatar Dnyaneshwar Bhadane Committed by Radhakrishna Sripada
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drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 



Driver refers to the platform Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

v2:
- Unrolled wrapper IS_ADLP_GRAPHICS_STEP and Replace
- Added IS_ALDERLAKE_P() && IS_GRAPHICS_STEP() (Jani/Tvrtko).

v3:
- Removed unused macros of display steps.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-11-dnyaneshwar.bhadane@intel.com
parent 48077b0b

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −1
Original line number Diff line number Diff line
@@ -3567,7 +3567,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.cdclk.table = dg2_cdclk_table;

	} else if (IS_ALDERLAKE_P(dev_priv)) {

		/* Wa_22011320316:adl-p[a0] */

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;

			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		} else if (IS_ADLP_RPLU(dev_priv)) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -3785,7 +3785,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte 
{

	u32 val;



	if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||

	if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||

	    pll->info->id != DPLL_ID_ICL_DPLL0)

		return;

	/*

drivers/gpu/drm/i915/display/intel_psr.c

+4 −4
Original line number Diff line number Diff line
@@ -748,7 +748,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	}



	/* Wa_22012278275:adl-p */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {

	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {

		static const u8 map[] = {

			2, /* 5 lines */

			1, /* 6 lines */
@@ -918,7 +918,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 
		return;



	/* Wa_16011303918:adl-p */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

		return;



	/*
@@ -1086,7 +1086,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");

		return false;

	}
@@ -1144,7 +1144,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 


	/* Wa_16011303918:adl-p */

	if (crtc_state->vrr.enable &&

	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

	    IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");

		return false;

drivers/gpu/drm/i915/display/skl_universal_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 
		return false;



	/* Wa_22011186057 */

	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))

	if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))

		return false;



	if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 
		return false;



	/* Wa_22011186057 */

	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))

	if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))

		return false;



	/* Wa_14013215631 */

drivers/gpu/drm/i915/i915_drv.h

+0 −7
Original line number Diff line number Diff line
@@ -661,13 +661,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
	(IS_ALDERLAKE_S(__i915) && \

	 IS_GRAPHICS_STEP(__i915, since, until))



#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \

	(IS_ALDERLAKE_P(__i915) && \

	 IS_DISPLAY_STEP(__i915, since, until))



#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \

	(IS_ALDERLAKE_P(__i915) && \

	 IS_GRAPHICS_STEP(__i915, since, until))



#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \

	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))