Commit cbfdfeba authored by zhangshuowen96's avatar zhangshuowen96
Browse files

drivers: misc: sdma-dae: support getting streamID 

kunpeng inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9W355


CVE: NA

----------------------------------------------------------------------

Add basic functions like: open, release, ioctl functions
of sdma char device, support 2 ioctl: IOCTL_SDMA_GET_
PROCESS_ID and IOCTL_SDMA_GET_STREAMID

Signed-off-by: default avatarzhangshuowen96 <zhangshuowen@hisilicon.com>
parent 60bf9d96

drivers/misc/sdma-dae/hisi_sdma.h

+46 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __HISI_SDMA_H__

#define __HISI_SDMA_H__
@@ -8,11 +8,56 @@ 


#define HISI_SDMA_DEVICE_NAME			"sdma"

#define HISI_SDMA_MAX_DEVS			4

#define HISI_SDMA_MAX_NODES			16



#define HISI_SDMA_MMAP_SQE			0

#define HISI_SDMA_MMAP_CQE			1

#define HISI_SDMA_MMAP_IO			2

#define HISI_SDMA_MMAP_SHMEM			3

#define HISI_SDMA_FSM_TIMEOUT			100



#define HISI_SDMA_CHANNEL_IOMEM_SIZE		0x1000

#define HISI_SDMA_SQ_ENTRY_SIZE			64UL

#define HISI_SDMA_CQ_ENTRY_SIZE			16UL

#define HISI_SDMA_SQ_LENGTH			(1U << 16)

#define HISI_SDMA_CQ_LENGTH			(1U << 16)



#define HISI_STARS_CHN_NUM			32

#define HISI_SDMA_DEFAULT_CHANNEL_NUM		(192 - HISI_STARS_CHN_NUM)

#define HISI_SDMA_SQ_SIZE			(HISI_SDMA_SQ_ENTRY_SIZE * HISI_SDMA_SQ_LENGTH)

#define HISI_SDMA_CQ_SIZE			(HISI_SDMA_CQ_ENTRY_SIZE * HISI_SDMA_CQ_LENGTH)

#define HISI_SDMA_REG_SIZE			4096

#define HISI_SDMA_CH_OFFSET			(HISI_STARS_CHN_NUM * HISI_SDMA_REG_SIZE)

#define HISI_SDMA_DEVICE_NAME_MAX		20

#define HISI_SDMA_MAX_ALLOC_SIZE		0x400000



struct chn_ioe_info {

	u32 ch_err_status;

	u32 ch_cqe_sqeid;

	u32 ch_cqe_status;

};



struct hisi_sdma_queue_info {

	u32    sq_head;

	u32    sq_tail;

	u32    cq_head;

	u32    cq_tail;

	u32    cq_vld;

	int    lock;

	u32    lock_pid;

	int    err_cnt;

	int    cqe_err[HISI_SDMA_SQ_LENGTH];

	u32    round_cnt[HISI_SDMA_SQ_LENGTH];

	struct chn_ioe_info ioe;

};



typedef int (*sdma_ioctl_funcs)(struct file *file, unsigned long arg);

struct hisi_sdma_ioctl_func_list {

	unsigned int cmd;

	sdma_ioctl_funcs ioctl_func;

};



#define IOCTL_SDMA_GET_PROCESS_ID	_IOR('s', 1, u32)

#define IOCTL_SDMA_GET_STREAMID		_IOR('s', 2, u32)



#endif

drivers/misc/sdma-dae/sdma_cdev.c

+135 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

// SPDX-License-Identifier: GPL-2.0-or-later

#include <linux/acpi.h>

#include <linux/delay.h>

#include <linux/dma-iommu.h>

#include <linux/platform_device.h>

#include <linux/sort.h>

#include "sdma_hal.h"



static struct hisi_sdma_global_info g_info;



struct file_open_data {

	int ida;

	u32 pasid;

	struct iommu_sva *handle;

	struct hisi_sdma_device *psdma_dev;

};



static int __do_sdma_open(struct hisi_sdma_device *psdma_dev, struct file *file)

{

	struct file_open_data *data;

	struct iommu_sva *handle;

	int id, ret;

	u32 pasid;



	id = ida_alloc(g_info.fd_ida, GFP_KERNEL);

	if (id < 0)

		return id;



	dev_dbg(&psdma_dev->pdev->dev, "%s: ida alloc id = %d\n", __func__, id);

	data = kmalloc_node(sizeof(struct file_open_data), GFP_KERNEL, psdma_dev->node_idx);

	if (!data) {

		ret = -ENOMEM;

		goto free_ida;

	}



	handle = iommu_sva_bind_device(&psdma_dev->pdev->dev, current->mm, NULL);

	if (IS_ERR(handle)) {

		dev_err(&psdma_dev->pdev->dev, "failed to bind sva, %ld\n", PTR_ERR(handle));

		ret = PTR_ERR(handle);

		goto free_privt_data;

	}



	pasid = iommu_sva_get_pasid(handle);

	if (pasid == IOMMU_PASID_INVALID) {

		ret = -ENODEV;

		goto sva_unbind;

	}



	data->ida = id;

	data->pasid = pasid;

	data->psdma_dev = psdma_dev;

	data->handle = handle;

	file->private_data = data;



	return 0;



sva_unbind:

	iommu_sva_unbind_device(handle);

free_privt_data:

	kfree(data);

free_ida:

	ida_free(g_info.fd_ida, id);

	return ret;

}



static int ioctl_sdma_get_process_id(struct file *file, unsigned long arg)

{

	u32 pid = (u32)current->tgid;



	if (copy_to_user((u32 __user *)(uintptr_t)arg, &pid, sizeof(u32)))

		return -EFAULT;



	return 0;

}



static int ioctl_sdma_get_streamid(struct file *file, unsigned long arg)

{

	struct file_open_data *data = file->private_data;

	struct hisi_sdma_device *pdev = data->psdma_dev;

	u32 streamid = pdev->streamid;



	if (copy_to_user((u32 __user *)(uintptr_t)arg, &streamid, sizeof(u32)))

		return -EFAULT;



	return 0;

}



struct hisi_sdma_ioctl_func_list g_ioctl_funcs[] = {

	{IOCTL_SDMA_GET_PROCESS_ID,        ioctl_sdma_get_process_id},

	{IOCTL_SDMA_GET_STREAMID,          ioctl_sdma_get_streamid},

};



static long sdma_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)

{

	int cmd_num;

	int i;



	cmd_num = sizeof(g_ioctl_funcs) / sizeof(struct hisi_sdma_ioctl_func_list);

	for (i = 0; i < cmd_num; i++) {

		if (g_ioctl_funcs[i].cmd == cmd)

			return g_ioctl_funcs[i].ioctl_func(file, arg);

	}



	return -ENOIOCTLCMD;

}



static int sdma_core_open(struct inode *inode, struct file *file)

{

	struct hisi_sdma_device *psdma_dev;

	dev_t sdma_dev;

	u32 sdma_idx;



	if (g_info.core_dev->sdma_device_num == 0) {

		pr_err("cannot find a sdma device\n");

		return -ENODEV;

	}

	sdma_dev = inode->i_rdev;

	sdma_idx = MINOR(sdma_dev);

	if (sdma_idx >= HISI_SDMA_MAX_DEVS) {

		pr_err("secondary device number overflow\n");

		return -ENODEV;

	}

	psdma_dev = g_info.core_dev->sdma_devices[sdma_idx];

	return __do_sdma_open(psdma_dev, file);

}



static int sdma_dev_release(struct inode *inode, struct file *file)

{

	struct file_open_data *data = file->private_data;



	if (data->handle) {

		iommu_sva_unbind_device(data->handle);

		data->handle = NULL;

	}



	ida_free(g_info.fd_ida, data->ida);

	kfree(file->private_data);

	return 0;

}



static const struct file_operations sdma_core_fops = {

	.owner = THIS_MODULE,

	.open = NULL,

	.open = sdma_core_open,

	.read = NULL,

	.release = NULL,

	.unlocked_ioctl = NULL,

	.release = sdma_dev_release,

	.unlocked_ioctl = sdma_dev_ioctl,

	.mmap = NULL,

};

drivers/misc/sdma-dae/sdma_hal.h

+110 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __HISI_SDMA_HAL_H__

#define __HISI_SDMA_HAL_H__
@@ -10,6 +10,9 @@ 
#include <linux/io.h>



#include "hisi_sdma.h"

#include "sdma_reg.h"



#define sdma_wmb() (asm volatile("dsb st" ::: "memory"))



/**

 * struct hisi_sdma_channel - Information about one channel in the SDMA device
@@ -42,7 +45,7 @@ struct hisi_sdma_channel { 
 * @channels: Pointer to the hisi_sdma_channel structure

 * @channel_map: Bitmap indicating the usage of the SDMA channel

 * @io_orig_base: I/O base address after mapping

 * @io_base: io_orig_base + 32 channel address offsets

 * @io_base: io_orig_base  32 channel address offsets

 * @base_addr: SDMA I/O base phyisical address

 * @name: SDMA device name in the /dev directory

 */
@@ -83,4 +86,109 @@ struct hisi_sdma_global_info { 


void sdma_cdev_init(struct cdev *cdev);

void sdma_info_sync_cdev(struct hisi_sdma_global_info *g_info);



static inline void chn_set_val(struct hisi_sdma_channel *pchan, int reg, u32 val, u32 mask)

{

	u32 reg_val = readl(pchan->io_base  reg);



	reg_val &= ~mask;

	reg_val |= FIELD_PREP(mask, val);



	writel(reg_val, pchan->io_base  reg);

}



static inline u32 chn_get_val(struct hisi_sdma_channel *pchan, int reg, u32 mask)

{

	u32 reg_val = readl(pchan->io_base  reg);



	return FIELD_GET(mask, reg_val);

}



static inline void sdma_channel_set_pause(struct hisi_sdma_channel *pchan)

{

	chn_set_val(pchan, HISI_SDMA_CH_TEST_REG, 1, HISI_SDMA_CH_PAUSE_MSK);

}



static inline bool sdma_channel_is_paused(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_STATUS_REG, HISI_SDMA_CHN_FSM_PAUSE_MSK) == 1;

}



static inline bool sdma_channel_is_idle(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_STATUS_REG, HISI_SDMA_CHN_FSM_IDLE_MSK) == 1;

}



static inline bool sdma_channel_is_quiescent(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_STATUS_REG, HISI_SDMA_CHN_FSM_QUIESCENT_MSK) == 1;

}



static inline void sdma_channel_write_reset(struct hisi_sdma_channel *pchan)

{

	chn_set_val(pchan, HISI_SDMA_CH_TEST_REG, 1, HISI_SDMA_CH_RESET_MSK);

}



static inline void sdma_channel_enable(struct hisi_sdma_channel *pchan)

{

	chn_set_val(pchan, HISI_SDMA_CH_CTRL_REG, 1, HISI_SDMA_CH_ENABLE_MSK);

}



static inline void sdma_channel_disable(struct hisi_sdma_channel *pchan)

{

	chn_set_val(pchan, HISI_SDMA_CH_CTRL_REG, 0, HISI_SDMA_CH_ENABLE_MSK);

}



static inline void sdma_channel_set_sq_size(struct hisi_sdma_channel *pchan, u32 size)

{

	U_SDMAM_CH_REGS_SDMAM_CH_SQ_ATTR reg_val = {0};



	reg_val.bits.sq_size = size;

	reg_val.bits.sq_shareability = HISI_SDMA_CH_SQ_SHARE_ATTR;

	reg_val.bits.sq_cacheability = HISI_SDMA_CH_SQ_CACHE_ATTR;



	chn_set_val(pchan, HISI_SDMA_CH_SQ_ATTR_REG, reg_val.u32, HISI_SDMA_U32_MSK);

}



static inline void sdma_channel_set_cq_size(struct hisi_sdma_channel *pchan, u32 size)

{

	U_SDMAM_CH_REGS_SDMAM_CH_CQ_ATTR reg_val = {0};



	reg_val.bits.cq_size = size;

	reg_val.bits.cq_shareability = HISI_SDMA_CH_CQ_SHARE_ATTR;

	reg_val.bits.cq_cacheability = HISI_SDMA_CH_CQ_CACHE_ATTR;



	chn_set_val(pchan, HISI_SDMA_CH_CQ_ATTR_REG, reg_val.u32, HISI_SDMA_U32_MSK);

}



static inline u32 sdma_channel_get_sq_tail(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_SQTDBR_REG, HISI_SDMA_U32_MSK);

}



static inline void sdma_channel_set_sq_tail(struct hisi_sdma_channel *pchan, u32 val)

{

	chn_set_val(pchan, HISI_SDMA_CH_SQTDBR_REG, val, HISI_SDMA_U32_MSK);

}



static inline u32 sdma_channel_get_sq_head(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_SQHDBR_REG, HISI_SDMA_U32_MSK);

}



static inline void sdma_channel_set_cq_head(struct hisi_sdma_channel *pchan, u32 val)

{

	chn_set_val(pchan, HISI_SDMA_CH_CQHDBR_REG, val, HISI_SDMA_U32_MSK);

}



static inline u32 sdma_channel_get_cq_tail(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_CQTDBR_REG, HISI_SDMA_U32_MSK);

}



static inline u32 sdma_channel_get_cq_head(struct hisi_sdma_channel *pchan)

{

	return chn_get_val(pchan, HISI_SDMA_CH_CQHDBR_REG, HISI_SDMA_U32_MSK);

}



#endif

drivers/misc/sdma-dae/sdma_main.c

+178 −2
Original line number Diff line number Diff line
@@ -10,10 +10,178 @@ 


#include "sdma_hal.h"



#define UPPER_SHIFT		32

#define MAX_INPUT_LENGTH	128



struct ida fd_ida;

struct hisi_sdma_core_device hisi_sdma_core_device = {0};

static struct class *sdma_class;



static bool sdma_channel_alloc_sq_cq(struct hisi_sdma_channel *pchan, u32 idx)

{

	int sync_size = sizeof(struct hisi_sdma_queue_info);

	struct page *page_list;



	if (idx >= HISI_SDMA_MAX_NODES) {

		pr_err("SDMA device id overflow, probe sdma%u failed!\n", idx);

		return false;

	}

	page_list = alloc_pages_node(idx, GFP_KERNEL | __GFP_ZERO, get_order(HISI_SDMA_SQ_SIZE));

	if (!page_list) {

		pr_err("channel%u: alloc sq page_list failed\n", pchan->idx);

		return false;

	}

	pchan->sq_base = (struct hisi_sdma_sq_entry *)page_to_virt(page_list);



	page_list = alloc_pages_node(idx, GFP_KERNEL | __GFP_ZERO, get_order(HISI_SDMA_CQ_SIZE));

	if (!page_list) {

		pr_err("channel%u: alloc cq page_list failed\n", pchan->idx);

		return false;

	}

	pchan->cq_base = (struct hisi_sdma_cq_entry *)page_to_virt(page_list);



	page_list = alloc_pages_node(idx, GFP_KERNEL | __GFP_ZERO, get_order(sync_size));

	if (!page_list) {

		pr_err("channel%u: alloc sync_info page_list failed\n", pchan->idx);

		return false;

	}

	pchan->sync_info_base = (struct hisi_sdma_queue_info *)page_to_virt(page_list);

	pchan->sync_info_base->cq_vld = 1;



	return true;

}



static void sdma_channel_init(struct hisi_sdma_channel *pchan)

{

	void __iomem *io_base = pchan->io_base;

	u64 sq_addr = virt_to_phys(pchan->sq_base);

	u64 cq_addr = virt_to_phys(pchan->cq_base);



	writel(sq_addr & 0xFFFFFFFF, io_base  HISI_SDMA_CH_SQBASER_L_REG);

	writel(sq_addr >> UPPER_SHIFT, io_base  HISI_SDMA_CH_SQBASER_H_REG);

	writel(cq_addr & 0xFFFFFFFF, io_base  HISI_SDMA_CH_CQBASER_L_REG);

	writel(cq_addr >> UPPER_SHIFT, io_base  HISI_SDMA_CH_CQBASER_H_REG);



	sdma_channel_set_sq_size(pchan, HISI_SDMA_SQ_LENGTH - 1);

	sdma_channel_set_cq_size(pchan, HISI_SDMA_CQ_LENGTH - 1);

	sdma_channel_set_sq_tail(pchan, 0);

	sdma_channel_set_cq_head(pchan, 0);



	sdma_channel_enable(pchan);

}



static void sdma_channel_reset_sq_cq(struct hisi_sdma_channel *pchan)

{

	u32 sq_head, sq_tail, cq_head, cq_tail;



	sq_head = sdma_channel_get_sq_head(pchan);

	sq_tail = sdma_channel_get_sq_tail(pchan);

	cq_head = sdma_channel_get_cq_head(pchan);

	cq_tail = sdma_channel_get_cq_tail(pchan);



	if (sq_head != sq_tail)

		sdma_channel_set_sq_tail(pchan, sq_head);



	if (cq_head != cq_tail)

		sdma_channel_set_cq_head(pchan, cq_tail);

}



static void sdma_channel_reset(struct hisi_sdma_channel *pchan)

{

	int i = 0;



	sdma_channel_reset_sq_cq(pchan);

	sdma_channel_set_pause(pchan);

	while (!sdma_channel_is_paused(pchan)) {

		mdelay(1);

		if (i > HISI_SDMA_FSM_TIMEOUT) {

			pr_warn("chn%u cannot get paused\n", pchan->idx);

			return;

		}

	}

	i = 0;

	while (!sdma_channel_is_quiescent(pchan)) {

		mdelay(1);

		if (i > HISI_SDMA_FSM_TIMEOUT) {

			pr_warn("chn%u cannot get quiescent\n", pchan->idx);

			return;

		}

	}

	i = 0;

	sdma_channel_write_reset(pchan);

	while (!sdma_channel_is_idle(pchan)) {

		mdelay(1);

		if (i > HISI_SDMA_FSM_TIMEOUT) {

			pr_warn("chn%u cannot get idle\n", pchan->idx);

			return;

		}

	}

}



static void sdma_free_all_sq_cq(struct hisi_sdma_device *psdma_dev)

{

	struct hisi_sdma_channel *pchan;

	int sync_size;

	int i;



	sync_size = sizeof(struct hisi_sdma_queue_info);



	for (i = psdma_dev->nr_channel - 1; i >= 0; i--) {

		pchan = psdma_dev->channels  i;

		if (pchan->io_base)

			sdma_channel_reset(pchan);

		if (pchan->sq_base)

			free_pages((uintptr_t)(void *)pchan->sq_base, get_order(HISI_SDMA_SQ_SIZE));

		if (pchan->cq_base)

			free_pages((uintptr_t)(void *)pchan->cq_base, get_order(HISI_SDMA_CQ_SIZE));

		if (pchan->sync_info_base)

			free_pages((uintptr_t)(void *)pchan->sync_info_base, get_order(sync_size));

	}

}



void sdma_destroy_channels(struct hisi_sdma_device *psdma_dev)

{

	if (!psdma_dev || !psdma_dev->channels)

		return;



	sdma_free_all_sq_cq(psdma_dev);

	kfree(psdma_dev->channels);

}



int sdma_init_channels(struct hisi_sdma_device *psdma_dev)

{

	u32 chn_num = psdma_dev->nr_channel;

	struct hisi_sdma_channel *pchan;

	u32 i;



	psdma_dev->channels = kcalloc_node(chn_num, sizeof(struct hisi_sdma_channel), GFP_KERNEL,

					   psdma_dev->node_idx);

	if (!psdma_dev->channels)

		return -ENOMEM;



	for (i = 0; i < chn_num; i++) {

		pchan = psdma_dev->channels  i;

		pchan->idx = i;

		pchan->pdev = psdma_dev;



		if (sdma_channel_alloc_sq_cq(pchan, psdma_dev->node_idx) == false)

			goto err_out;



		pchan->io_base = psdma_dev->io_base  i * HISI_SDMA_CHANNEL_IOMEM_SIZE;



		sdma_channel_disable(pchan);

		sdma_channel_init(pchan);

	}



	bitmap_set(psdma_dev->channel_map, 0, chn_num);



	return 0;



err_out:

	sdma_destroy_channels(psdma_dev);

	return -ENOMEM;

}



static int sdma_device_add(struct hisi_sdma_device *psdma_dev)

{

	u32 idx = psdma_dev->idx;
@@ -45,7 +213,7 @@ static int sdma_device_add(struct hisi_sdma_device *psdma_dev) 
		goto out_err;

	}



	hisi_sdma_core_device.sdma_device_num++;

	hisi_sdma_core_device.sdma_device_num;



	return 0;
@@ -117,7 +285,13 @@ static int sdma_init_device_info(struct hisi_sdma_device *psdma_dev) 
		iounmap(psdma_dev->io_orig_base);

		return -ENOMEM;

	}

	psdma_dev->io_base = psdma_dev->io_orig_base + HISI_SDMA_CH_OFFSET;

	psdma_dev->io_base = psdma_dev->io_orig_base  HISI_SDMA_CH_OFFSET;

	ret = sdma_init_channels(psdma_dev);

	if (ret < 0) {

		iounmap(psdma_dev->common_base);

		iounmap(psdma_dev->io_orig_base);

		return ret;

	}



	return 0;

}
@@ -191,6 +365,7 @@ static int sdma_device_probe(struct platform_device *pdev) 
	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);

deinit_device:

	sdma_destroy_channels(psdma_dev);

	iounmap(psdma_dev->common_base);

	iounmap(psdma_dev->io_orig_base);

free_dev:
@@ -207,6 +382,7 @@ static int sdma_device_remove(struct platform_device *pdev) 
	device_destroy(sdma_class, MKDEV(hisi_sdma_core_device.sdma_major, psdma_dev->idx));

	cdev_del(&psdma_dev->cdev);



	sdma_destroy_channels(psdma_dev);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);

	iounmap(psdma_dev->io_orig_base);

drivers/misc/sdma-dae/sdma_reg.h

0 → 100644
+68 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */



#ifndef __HISI_SDMA_REG_H__

#define __HISI_SDMA_REG_H__



/* HISI_SDMA_CH_REGS Registers' Definitions */

#define HISI_SDMA_CH_CTRL_REG			0x0

#define HISI_SDMA_CH_TEST_REG			0x4

#define HISI_SDMA_IRQ_STATUS			0xC

#define HISI_SDMA_CH_IRQ_CTRL_REG		0x10

#define HISI_SDMA_CH_CQE_STATUS_REG		0x18

#define HISI_SDMA_CH_STATUS_REG			0x1C

#define HISI_SDMA_CH_SQBASER_L_REG		0x40

#define HISI_SDMA_CH_SQBASER_H_REG		0x44

#define HISI_SDMA_CH_SQ_ATTR_REG		0x48

#define HISI_SDMA_CH_SQTDBR_REG			0x4C

#define HISI_SDMA_CH_SQHDBR_REG			0x50

#define HISI_SDMA_CH_CQBASER_L_REG		0x80

#define HISI_SDMA_CH_CQBASER_H_REG		0x84

#define HISI_SDMA_CH_CQ_ATTR_REG		0x88

#define HISI_SDMA_CH_CQTDBR_REG			0x8C

#define HISI_SDMA_CH_CQHDBR_REG			0x90



#define HISI_SDMA_CH_DFX_REG			0x300



#define HISI_SDMA_U32_MSK			GENMASK(31, 0)

/* REG_FILED_MASK IN HISI_SDMA_CH_CTRL_REG */

#define HISI_SDMA_CH_ENABLE_MSK			GENMASK(0, 0)



/* REG_FILED_MASK IN HISI_SDMA_CH_TEST_REG */

#define HISI_SDMA_CH_PAUSE_MSK			GENMASK(0, 0)

#define HISI_SDMA_CH_RESET_MSK			GENMASK(2, 2)



/* HISI_SDMA_CH_FSM_STATUS VAL */

#define HISI_SDMA_CHN_FSM_IDLE_MSK		GENMASK(0, 0)

#define HISI_SDMA_CHN_FSM_PAUSE_MSK		GENMASK(3, 3)

#define HISI_SDMA_CHN_FSM_QUIESCENT_MSK		GENMASK(4, 4)



/* HISI_SDMA_IRQ_STATUS */

#define HISI_SDMA_CHN_IRQ_STATUS_MSK		GENMASK(27, 20)

#define HISI_SDMA_CHN_CQE_STATUS_MSK		GENMASK(5, 1)

#define HISI_SDMA_CHN_CQE_SQEID_MSK		GENMASK(21, 6)



/* HISI_SDMA_CH_DFX_INFO0 */

#define HISI_SDMA_CHN_NORMAL_SQE_CNT_MSK	GENMASK(31, 16)

#define HISI_SDMA_CHN_ERROR_SQE_CNT_MSK		GENMASK(15, 0)



/* HISI_SDMA_SQ_ATTR */

#define HISI_SDMA_CH_SQ_SHARE_ATTR		0x1

#define HISI_SDMA_CH_SQ_CACHE_ATTR		0x7



/* HISI_SDMA_CQ_ATTR */

#define HISI_SDMA_CH_CQ_SHARE_ATTR		0x1

#define HISI_SDMA_CH_CQ_CACHE_ATTR		0x7



#endif



#ifndef __HISI_SDMA_COMMON_REG_OFFSET_H__

#define __HISI_SDMA_COMMON_REG_OFFSET_H__



#define HISI_SDMA_SMMU_BYPASS_PART0		0x3c8

#define HISI_SDMA_SMMU_BYPASS_PART_SIZE		0x4



#define HISI_SDMA_DMA_MPAMID_CFG		0x50c

#define HISI_SDMA_DFX_FEATURE_EN		0x544

#define HISI_SDMA_ERR_STATUSL			0x2010



#endif