Commit cbeee6ca authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Fix icelakex cstate metrics 

Apply cstate fix from:

https://github.com/intel/event-converter-for-linux-perf/



so that metrics for cstates that exist on the particular architecture
are generated. This corrects issues with metric testing.

Also correct topic of ASSISTS.ANY event.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-2-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2c77f36a

tools/perf/pmu-events/arch/x86/icelakex/cache.json

+1 −30
Original line number Diff line number Diff line
@@ -665,7 +665,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -677,7 +676,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -689,7 +687,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1008000004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -701,7 +698,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x808000004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -713,7 +709,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -725,7 +720,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -737,7 +731,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x4003C0001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -749,7 +742,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x8003C0001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -761,7 +753,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1030000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -773,7 +764,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x830000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -785,7 +775,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1008000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -797,7 +786,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x808000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -809,7 +797,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -821,7 +808,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -833,7 +819,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1008000002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -845,7 +830,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x808000002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -857,7 +841,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0400",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -869,7 +852,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x80082380",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -881,7 +863,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C27F0",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -893,7 +874,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F003C0477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -905,7 +885,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -917,7 +896,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x4003C0477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -929,7 +907,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x8003C0477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -941,7 +918,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1830000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -953,7 +929,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1030000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -965,7 +940,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x830000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -977,7 +951,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1008000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -989,7 +962,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x808000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -1001,7 +973,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x80080800",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json

+3 −21
Original line number Diff line number Diff line
@@ -475,10 +475,10 @@ 
        "MetricName": "IpFarBranch"

    },

    {

        "BriefDescription": "C3 residency percent per core",

        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",

        "BriefDescription": "C1 residency percent per core",

        "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C3_Core_Residency"

        "MetricName": "C1_Core_Residency"

    },

    {

        "BriefDescription": "C6 residency percent per core",
@@ -486,34 +486,16 @@ 
        "MetricGroup": "Power",

        "MetricName": "C6_Core_Residency"

    },

    {

        "BriefDescription": "C7 residency percent per core",

        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C7_Core_Residency"

    },

    {

        "BriefDescription": "C2 residency percent per package",

        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C2_Pkg_Residency"

    },

    {

        "BriefDescription": "C3 residency percent per package",

        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C3_Pkg_Residency"

    },

    {

        "BriefDescription": "C6 residency percent per package",

        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C6_Pkg_Residency"

    },

    {

        "BriefDescription": "C7 residency percent per package",

        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",

        "MetricGroup": "Power",

        "MetricName": "C7_Pkg_Residency"

    }

]

tools/perf/pmu-events/arch/x86/icelakex/memory.json

+1 −20
Original line number Diff line number Diff line
@@ -159,7 +159,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -171,7 +170,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -183,7 +181,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -195,7 +192,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -207,7 +203,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F3FC00002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -219,7 +214,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F04400002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -231,7 +225,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00400",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -243,7 +236,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400400",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -255,7 +247,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x94002380",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -267,7 +258,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x84002380",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -279,7 +269,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x84000002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -291,7 +280,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC08000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -303,7 +291,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84408000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -315,7 +302,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F844027F0",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -327,7 +313,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F3FC00477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -339,7 +324,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F04400477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -351,7 +335,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x70CC00477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -363,7 +346,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x94000800",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -375,7 +357,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x84000800",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

tools/perf/pmu-events/arch/x86/icelakex/other.json

+15 −55

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/icelakex/pipeline.json

+13 −1
Original line number Diff line number Diff line
@@ -12,6 +12,18 @@ 
        "Speculative": "1",

        "UMask": "0x9"

    },

    {

        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.ANY",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x7"

    },

    {

        "BriefDescription": "All branch instructions retired.",

        "CollectPEBSRecord": "2",