Commit cbcddaa3 authored by Andrew Cooper's avatar Andrew Cooper Committed by Borislav Petkov
Browse files

perf/x86/rapl: Use CPUID bit on AMD and Hygon parts 



AMD and Hygon CPUs have a CPUID bit for RAPL.  Drop the fam17h suffix as
it is stale already.

Make use of this instead of a model check to work more nicely in virtual
environments where RAPL typically isn't available.

 [ bp: drop the ../cpu/powerflags.c hunk which is superfluous as the
   "rapl" bit name appears already in flags. ]

Signed-off-by: default avatarAndrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20210514135920.16093-1-andrew.cooper3@citrix.com
parent 280b68a3

arch/x86/events/rapl.c

+2 −4
Original line number Diff line number Diff line
@@ -764,13 +764,14 @@ static struct rapl_model model_spr = { 
	.rapl_msrs      = intel_rapl_spr_msrs,

};



static struct rapl_model model_amd_fam17h = {

static struct rapl_model model_amd_hygon = {

	.events		= BIT(PERF_RAPL_PKG),

	.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,

	.rapl_msrs      = amd_rapl_msrs,

};



static const struct x86_cpu_id rapl_model_match[] __initconst = {

	X86_MATCH_FEATURE(X86_FEATURE_RAPL,		&model_amd_hygon),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&model_snb),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&model_snbep),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&model_snb),
@@ -803,9 +804,6 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&model_spr),

	X86_MATCH_VENDOR_FAM(AMD,	0x17,		&model_amd_fam17h),

	X86_MATCH_VENDOR_FAM(HYGON,	0x18,		&model_amd_fam17h),

	X86_MATCH_VENDOR_FAM(AMD,	0x19,		&model_amd_fam17h),

	{},

};

MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ 
#define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */

#define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */

/* free					( 3*32+29) */

#define X86_FEATURE_RAPL		( 3*32+29) /* AMD/Hygon RAPL interface */

#define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */

#define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */

arch/x86/kernel/cpu/amd.c

+4 −0
Original line number Diff line number Diff line
@@ -646,6 +646,10 @@ static void early_init_amd(struct cpuinfo_x86 *c) 
	if (c->x86_power & BIT(12))

		set_cpu_cap(c, X86_FEATURE_ACC_POWER);



	/* Bit 14 indicates the Runtime Average Power Limit interface. */

	if (c->x86_power & BIT(14))

		set_cpu_cap(c, X86_FEATURE_RAPL);



#ifdef CONFIG_X86_64

	set_cpu_cap(c, X86_FEATURE_SYSCALL32);

#else

arch/x86/kernel/cpu/hygon.c

+4 −0
Original line number Diff line number Diff line
@@ -260,6 +260,10 @@ static void early_init_hygon(struct cpuinfo_x86 *c) 
	if (c->x86_power & BIT(12))

		set_cpu_cap(c, X86_FEATURE_ACC_POWER);



	/* Bit 14 indicates the Runtime Average Power Limit interface. */

	if (c->x86_power & BIT(14))

		set_cpu_cap(c, X86_FEATURE_RAPL);



#ifdef CONFIG_X86_64

	set_cpu_cap(c, X86_FEATURE_SYSCALL32);

#endif