Commit cbaf0cf0 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation 



This converts TRBBASER_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-11-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 66696977

arch/arm64/include/asm/sysreg.h

+0 −3
Original line number Diff line number Diff line
@@ -227,14 +227,11 @@ 


/*** End of Statistical Profiling Extension ***/



#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)

#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)

#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)

#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)

#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)



#define TRBBASER_EL1_BASE_MASK		GENMASK_ULL(63, 12)

#define TRBBASER_EL1_BASE_SHIFT		12

#define TRBSR_EL1_EC_MASK		GENMASK(31, 26)

#define TRBSR_EL1_EC_SHIFT		26

#define TRBSR_EL1_IRQ			BIT(22)

arch/arm64/tools/sysreg

+5 −0
Original line number Diff line number Diff line
@@ -2277,3 +2277,8 @@ EndSysreg 
Sysreg	TRBPTR_EL1	3	0	9	11	1

Field	63:0	PTR

EndSysreg



Sysreg	TRBBASER_EL1	3	0	9	11	2

Field	63:12	BASE

Res0	11:0

EndSysreg