Unverified Commit cbad7a99 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!940 net: hns3: related bugfixes, refactoring, and cleanup 

Merge Pull Request from: @svishen 
 
This pull request for hns3 related bugfixes, refactoring, and cleanup

(1)perf: pmu: fix set wrong filter mode for running events issue
(2)net: hns3: fix GRE checksum offload issue
(3)net: hns3: fix the imp capability bit cannot exceed 32 bits issue
(4)net: hns3: add tm flush when setting tm
(5)net: hns3: refactor hclge_update_desc_vfid for extension
(6)net: hns3: fix strncpy() not using dest-buf length as length issue
(7)net: hns3: restore user pause configure when disable autoneg

issue:
https://gitee.com/openeuler/kernel/issues/I7B8SA 
 
Link:https://gitee.com/openeuler/kernel/pulls/940

 

Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 6e15a541 ae9425eb

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+6 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <linux/pci.h>

#include <linux/pkt_sched.h>

#include <linux/types.h>

#include <linux/bitmap.h>

#include <net/pkt_cls.h>



#define HNAE3_MOD_VERSION "1.0"
@@ -104,6 +105,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_WOL_B,

	HNAE3_DEV_SUPPORT_VF_FAULT_B,

	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,

	HNAE3_DEV_SUPPORT_TM_FLUSH_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -178,6 +180,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_notify_pkt_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)



#define hnae3_ae_dev_tm_flush_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};
@@ -421,7 +426,7 @@ struct hnae3_ae_dev { 
	unsigned long hw_err_reset_req;

	struct hnae3_dev_specs dev_specs;

	u32 dev_version;

	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];

	DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);

	void *priv;

};

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+19 −3
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},

	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},

	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},

	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
@@ -172,6 +173,20 @@ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},

};



static void

hclge_comm_capability_to_bitmap(unsigned long *bitmap, __le32 *caps)

{

	const unsigned int words = HCLGE_COMM_QUERY_CAP_LENGTH;

	u32 val[HCLGE_COMM_QUERY_CAP_LENGTH];

	unsigned int i;



	for (i = 0; i < words; i++)

		val[i] = __le32_to_cpu(caps[i]);



	bitmap_from_arr32(bitmap, val,

			  HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));

}



static void

hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,

			    struct hclge_comm_query_version_cmd *cmd)
@@ -180,11 +195,12 @@ hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf, 
				is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps;

	u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) :

				ARRAY_SIZE(hclge_vf_cmd_caps);

	u32 caps, i;

	DECLARE_BITMAP(caps, HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));

	u32 i;



	caps = __le32_to_cpu(cmd->caps[0]);

	hclge_comm_capability_to_bitmap(caps, cmd->caps);

	for (i = 0; i < size; i++)

		if (hnae3_get_bit(caps, caps_map[i].imp_bit))

		if (test_bit(caps_map[i].imp_bit, caps))

			set_bit(caps_map[i].local_bit, ae_dev->caps);

}

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+2 −0
Original line number Diff line number Diff line
@@ -153,6 +153,7 @@ enum hclge_opcode_type { 
	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,

	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,

	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,

	HCLGE_OPC_TM_FLUSH		= 0x0872,



	/* Packet buffer allocate commands */

	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
@@ -350,6 +351,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_LANE_NUM_B = 27,

	HCLGE_COMM_CAP_WOL_B = 28,

	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,

	HCLGE_COMM_CAP_TM_FLUSH_B = 31,

};



enum HCLGE_COMM_API_CAP_BITS {

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+27 −7
Original line number Diff line number Diff line
@@ -415,6 +415,9 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 
	}, {

		.name = "support vf fault detect",

		.cap_bit = HNAE3_DEV_SUPPORT_VF_FAULT_B,

	}, {

		.name = "support tm flush",

		.cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,

	}

};
@@ -442,19 +445,36 @@ static void hns3_dbg_fill_content(char *content, u16 len, 
				  const struct hns3_dbg_item *items,

				  const char **result, u16 size)

{

#define HNS3_DBG_LINE_END_LEN	2

	char *pos = content;

	u16 item_len;

	u16 i;



	if (!len) {

		return;

	} else if (len <= HNS3_DBG_LINE_END_LEN) {

		*pos++ = '\0';

		return;

	}



	memset(content, ' ', len);

	for (i = 0; i < size; i++) {

		if (result)

			strncpy(pos, result[i], strlen(result[i]));

		else

			strncpy(pos, items[i].name, strlen(items[i].name));

	len -= HNS3_DBG_LINE_END_LEN;



		pos += strlen(items[i].name) + items[i].interval;

	for (i = 0; i < size; i++) {

		item_len = strlen(items[i].name) + items[i].interval;

		if (len < item_len)

			break;



		if (result) {

			if (item_len < strlen(result[i]))

				break;

			memcpy(pos, result[i], strlen(result[i]));

		} else {

			memcpy(pos, items[i].name, strlen(items[i].name));

		}

		pos += item_len;

		len -= item_len;

	}



	*pos++ = '\n';

	*pos++ = '\0';

}

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+8 −4
Original line number Diff line number Diff line
@@ -3547,15 +3547,19 @@ static void hns3_set_default_feature(struct net_device *netdev) 


	netdev->priv_flags |= IFF_UNICAST_FLT;



	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;



	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |

		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |

		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |

		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |

		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |

		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 |

		NETIF_F_GSO_UDP_TUNNEL |

		NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;



	if (pdev->revision == HNAE3_DEVICE_VERSION_V2) {

		netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;

		netdev->features |= NETIF_F_GSO_GRE_CSUM;

		netdev->features |= NETIF_F_GSO_GRE;

	}



	if (hnae3_ae_dev_gro_supported(ae_dev))

		netdev->features |= NETIF_F_GRO_HW;