Commit cb9d4f00 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-qcom' into next 

* pci/host-qcom:
  PCI: qcom: Add support for IPQ8074 PCIe controller
  dt-bindings: PCI: qcom: Add support for IPQ8074
  PCI: qcom: Use block IP version for operations
  PCI: qcom: Explicitly request exclusive reset control
  PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expanders
parents 73646b7f 5d76117f

Documentation/devicetree/bindings/pci/qcom,pcie.txt

+23 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
			- "qcom,pcie-apq8084" for apq8084

			- "qcom,pcie-msm8996" for msm8996 or apq8096

			- "qcom,pcie-ipq4019" for ipq4019

			- "qcom,pcie-ipq8074" for ipq8074



- reg:

	Usage: required
@@ -105,6 +106,16 @@ 
			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock



- clock-names:

	Usage: required for ipq8074

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	PCIe to SysNOC BIU clock

			- "axi_m"	AXI Master clock

			- "axi_s"	AXI Slave clock

			- "ahb"		AHB clock

			- "aux"		Auxiliary clock



- resets:

	Usage: required

	Value type: <prop-encoded-array>
@@ -144,6 +155,18 @@ 
			- "ahb"			AHB reset

			- "phy_ahb"		PHY AHB reset



- reset-names:

	Usage: required for ipq8074

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pipe"		PIPE reset

			- "sleep"		Sleep reset

			- "sticky"		Core Sticky reset

			- "axi_m"		AXI Master reset

			- "axi_s"		AXI Slave reset

			- "ahb"			AHB Reset

			- "axi_m_sticky"	AXI Master Sticky reset



- power-domains:

	Usage: required for apq8084 and msm8996/apq8096

	Value type: <prop-encoded-array>

drivers/pci/dwc/pcie-qcom.c

+300 −87
Original line number Diff line number Diff line
@@ -37,6 +37,20 @@ 
#include "pcie-designware.h"



#define PCIE20_PARF_SYS_CTRL			0x00

#define MST_WAKEUP_EN				BIT(13)

#define SLV_WAKEUP_EN				BIT(12)

#define MSTR_ACLK_CGC_DIS			BIT(10)

#define SLV_ACLK_CGC_DIS			BIT(9)

#define CORE_CLK_CGC_DIS			BIT(6)

#define AUX_PWR_DET				BIT(4)

#define L23_CLK_RMV_DIS				BIT(2)

#define L1_CLK_RMV_DIS				BIT(1)



#define PCIE20_COMMAND_STATUS			0x04

#define CMD_BME_VAL				0x4

#define PCIE20_DEVICE_CONTROL2_STATUS2		0x98

#define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10



#define PCIE20_PARF_PHY_CTRL			0x40

#define PCIE20_PARF_PHY_REFCLK			0x4C

#define PCIE20_PARF_DBI_BASE_ADDR		0x168
@@ -58,10 +72,22 @@ 
#define CFG_BRIDGE_SB_INIT			BIT(0)



#define PCIE20_CAP				0x70

#define PCIE20_CAP_LINK_CAPABILITIES		(PCIE20_CAP + 0xC)

#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT	(BIT(10) | BIT(11))

#define PCIE20_CAP_LINK_1			(PCIE20_CAP + 0x14)

#define PCIE_CAP_LINK1_VAL			0x2FD7F



#define PCIE20_PARF_Q2A_FLUSH			0x1AC



#define PCIE20_MISC_CONTROL_1_REG		0x8BC

#define DBI_RO_WR_EN				1



#define PERST_DELAY_US				1000



struct qcom_pcie_resources_v0 {

#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358

#define SLV_ADDR_SPACE_SZ			0x10000000



struct qcom_pcie_resources_2_1_0 {

	struct clk *iface_clk;

	struct clk *core_clk;

	struct clk *phy_clk;
@@ -75,7 +101,7 @@ struct qcom_pcie_resources_v0 { 
	struct regulator *vdda_refclk;

};



struct qcom_pcie_resources_v1 {

struct qcom_pcie_resources_1_0_0 {

	struct clk *iface;

	struct clk *aux;

	struct clk *master_bus;
@@ -84,7 +110,7 @@ struct qcom_pcie_resources_v1 { 
	struct regulator *vdda;

};



struct qcom_pcie_resources_v2 {

struct qcom_pcie_resources_2_3_2 {

	struct clk *aux_clk;

	struct clk *master_clk;

	struct clk *slave_clk;
@@ -92,7 +118,7 @@ struct qcom_pcie_resources_v2 { 
	struct clk *pipe_clk;

};



struct qcom_pcie_resources_v3 {

struct qcom_pcie_resources_2_4_0 {

	struct clk *aux_clk;

	struct clk *master_clk;

	struct clk *slave_clk;
@@ -110,11 +136,21 @@ struct qcom_pcie_resources_v3 { 
	struct reset_control *phy_ahb_reset;

};



struct qcom_pcie_resources_2_3_3 {

	struct clk *iface;

	struct clk *axi_m_clk;

	struct clk *axi_s_clk;

	struct clk *ahb_clk;

	struct clk *aux_clk;

	struct reset_control *rst[7];

};



union qcom_pcie_resources {

	struct qcom_pcie_resources_v0 v0;

	struct qcom_pcie_resources_v1 v1;

	struct qcom_pcie_resources_v2 v2;

	struct qcom_pcie_resources_v3 v3;

	struct qcom_pcie_resources_1_0_0 v1_0_0;

	struct qcom_pcie_resources_2_1_0 v2_1_0;

	struct qcom_pcie_resources_2_3_2 v2_3_2;

	struct qcom_pcie_resources_2_3_3 v2_3_3;

	struct qcom_pcie_resources_2_4_0 v2_4_0;

};



struct qcom_pcie;
@@ -142,13 +178,13 @@ struct qcom_pcie { 


static void qcom_ep_reset_assert(struct qcom_pcie *pcie)

{

	gpiod_set_value(pcie->reset, 1);

	gpiod_set_value_cansleep(pcie->reset, 1);

	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);

}



static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)

{

	gpiod_set_value(pcie->reset, 0);

	gpiod_set_value_cansleep(pcie->reset, 0);

	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);

}
@@ -173,7 +209,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 
	return dw_pcie_wait_for_link(pci);

}



static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)

static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;
@@ -183,9 +219,9 @@ static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie) 
	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);

}



static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)

static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;

	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;
@@ -213,29 +249,29 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) 
	if (IS_ERR(res->phy_clk))

		return PTR_ERR(res->phy_clk);



	res->pci_reset = devm_reset_control_get(dev, "pci");

	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");

	if (IS_ERR(res->pci_reset))

		return PTR_ERR(res->pci_reset);



	res->axi_reset = devm_reset_control_get(dev, "axi");

	res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");

	if (IS_ERR(res->axi_reset))

		return PTR_ERR(res->axi_reset);



	res->ahb_reset = devm_reset_control_get(dev, "ahb");

	res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");

	if (IS_ERR(res->ahb_reset))

		return PTR_ERR(res->ahb_reset);



	res->por_reset = devm_reset_control_get(dev, "por");

	res->por_reset = devm_reset_control_get_exclusive(dev, "por");

	if (IS_ERR(res->por_reset))

		return PTR_ERR(res->por_reset);



	res->phy_reset = devm_reset_control_get(dev, "phy");

	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");

	return PTR_ERR_OR_ZERO(res->phy_reset);

}



static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)

static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;

	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;



	reset_control_assert(res->pci_reset);

	reset_control_assert(res->axi_reset);
@@ -250,9 +286,9 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie) 
	regulator_disable(res->vdda_refclk);

}



static int qcom_pcie_init_v0(struct qcom_pcie *pcie)

static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;

	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	u32 val;
@@ -368,9 +404,9 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie) 
	return ret;

}



static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)

static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;
@@ -394,13 +430,13 @@ static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) 
	if (IS_ERR(res->slave_bus))

		return PTR_ERR(res->slave_bus);



	res->core = devm_reset_control_get(dev, "core");

	res->core = devm_reset_control_get_exclusive(dev, "core");

	return PTR_ERR_OR_ZERO(res->core);

}



static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)

static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;



	reset_control_assert(res->core);

	clk_disable_unprepare(res->slave_bus);
@@ -410,9 +446,9 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie) 
	regulator_disable(res->vdda);

}



static int qcom_pcie_init_v1(struct qcom_pcie *pcie)

static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int ret;
@@ -478,7 +514,7 @@ static int qcom_pcie_init_v1(struct qcom_pcie *pcie) 
	return ret;

}



static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)

static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;
@@ -488,9 +524,9 @@ static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie) 
	writel(val, pcie->parf + PCIE20_PARF_LTSSM);

}



static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)

static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;
@@ -514,9 +550,9 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) 
	return PTR_ERR_OR_ZERO(res->pipe_clk);

}



static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)

static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;



	clk_disable_unprepare(res->slave_clk);

	clk_disable_unprepare(res->master_clk);
@@ -524,16 +560,16 @@ static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie) 
	clk_disable_unprepare(res->aux_clk);

}



static void qcom_pcie_post_deinit_v2(struct qcom_pcie *pcie)

static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;



	clk_disable_unprepare(res->pipe_clk);

}



static int qcom_pcie_init_v2(struct qcom_pcie *pcie)

static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	u32 val;
@@ -596,9 +632,9 @@ static int qcom_pcie_init_v2(struct qcom_pcie *pcie) 
	return ret;

}



static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)

static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int ret;
@@ -612,9 +648,9 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie) 
	return 0;

}



static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)

static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v3 *res = &pcie->res.v3;

	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;
@@ -630,60 +666,64 @@ static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie) 
	if (IS_ERR(res->slave_clk))

		return PTR_ERR(res->slave_clk);



	res->axi_m_reset = devm_reset_control_get(dev, "axi_m");

	res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");

	if (IS_ERR(res->axi_m_reset))

		return PTR_ERR(res->axi_m_reset);



	res->axi_s_reset = devm_reset_control_get(dev, "axi_s");

	res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");

	if (IS_ERR(res->axi_s_reset))

		return PTR_ERR(res->axi_s_reset);



	res->pipe_reset = devm_reset_control_get(dev, "pipe");

	res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");

	if (IS_ERR(res->pipe_reset))

		return PTR_ERR(res->pipe_reset);



	res->axi_m_vmid_reset = devm_reset_control_get(dev, "axi_m_vmid");

	res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,

								 "axi_m_vmid");

	if (IS_ERR(res->axi_m_vmid_reset))

		return PTR_ERR(res->axi_m_vmid_reset);



	res->axi_s_xpu_reset = devm_reset_control_get(dev, "axi_s_xpu");

	res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,

								"axi_s_xpu");

	if (IS_ERR(res->axi_s_xpu_reset))

		return PTR_ERR(res->axi_s_xpu_reset);



	res->parf_reset = devm_reset_control_get(dev, "parf");

	res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");

	if (IS_ERR(res->parf_reset))

		return PTR_ERR(res->parf_reset);



	res->phy_reset = devm_reset_control_get(dev, "phy");

	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");

	if (IS_ERR(res->phy_reset))

		return PTR_ERR(res->phy_reset);



	res->axi_m_sticky_reset = devm_reset_control_get(dev, "axi_m_sticky");

	res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,

								   "axi_m_sticky");

	if (IS_ERR(res->axi_m_sticky_reset))

		return PTR_ERR(res->axi_m_sticky_reset);



	res->pipe_sticky_reset = devm_reset_control_get(dev, "pipe_sticky");

	res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,

								  "pipe_sticky");

	if (IS_ERR(res->pipe_sticky_reset))

		return PTR_ERR(res->pipe_sticky_reset);



	res->pwr_reset = devm_reset_control_get(dev, "pwr");

	res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");

	if (IS_ERR(res->pwr_reset))

		return PTR_ERR(res->pwr_reset);



	res->ahb_reset = devm_reset_control_get(dev, "ahb");

	res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");

	if (IS_ERR(res->ahb_reset))

		return PTR_ERR(res->ahb_reset);



	res->phy_ahb_reset = devm_reset_control_get(dev, "phy_ahb");

	res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");

	if (IS_ERR(res->phy_ahb_reset))

		return PTR_ERR(res->phy_ahb_reset);



	return 0;

}



static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)

static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v3 *res = &pcie->res.v3;

	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;



	reset_control_assert(res->axi_m_reset);

	reset_control_assert(res->axi_s_reset);
@@ -699,9 +739,9 @@ static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie) 
	clk_disable_unprepare(res->slave_clk);

}



static int qcom_pcie_init_v3(struct qcom_pcie *pcie)

static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v3 *res = &pcie->res.v3;

	struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	u32 val;
@@ -891,6 +931,166 @@ static int qcom_pcie_init_v3(struct qcom_pcie *pcie) 
	return ret;

}



static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int i;

	const char *rst_names[] = { "axi_m", "axi_s", "pipe",

				    "axi_m_sticky", "sticky",

				    "ahb", "sleep", };



	res->iface = devm_clk_get(dev, "iface");

	if (IS_ERR(res->iface))

		return PTR_ERR(res->iface);



	res->axi_m_clk = devm_clk_get(dev, "axi_m");

	if (IS_ERR(res->axi_m_clk))

		return PTR_ERR(res->axi_m_clk);



	res->axi_s_clk = devm_clk_get(dev, "axi_s");

	if (IS_ERR(res->axi_s_clk))

		return PTR_ERR(res->axi_s_clk);



	res->ahb_clk = devm_clk_get(dev, "ahb");

	if (IS_ERR(res->ahb_clk))

		return PTR_ERR(res->ahb_clk);



	res->aux_clk = devm_clk_get(dev, "aux");

	if (IS_ERR(res->aux_clk))

		return PTR_ERR(res->aux_clk);



	for (i = 0; i < ARRAY_SIZE(rst_names); i++) {

		res->rst[i] = devm_reset_control_get(dev, rst_names[i]);

		if (IS_ERR(res->rst[i]))

			return PTR_ERR(res->rst[i]);

	}



	return 0;

}



static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;



	clk_disable_unprepare(res->iface);

	clk_disable_unprepare(res->axi_m_clk);

	clk_disable_unprepare(res->axi_s_clk);

	clk_disable_unprepare(res->ahb_clk);

	clk_disable_unprepare(res->aux_clk);

}



static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int i, ret;

	u32 val;



	for (i = 0; i < ARRAY_SIZE(res->rst); i++) {

		ret = reset_control_assert(res->rst[i]);

		if (ret) {

			dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);

			return ret;

		}

	}



	usleep_range(2000, 2500);



	for (i = 0; i < ARRAY_SIZE(res->rst); i++) {

		ret = reset_control_deassert(res->rst[i]);

		if (ret) {

			dev_err(dev, "reset #%d deassert failed (%d)\n", i,

				ret);

			return ret;

		}

	}



	/*

	 * Don't have a way to see if the reset has completed.

	 * Wait for some time.

	 */

	usleep_range(2000, 2500);



	ret = clk_prepare_enable(res->iface);

	if (ret) {

		dev_err(dev, "cannot prepare/enable core clock\n");

		goto err_clk_iface;

	}



	ret = clk_prepare_enable(res->axi_m_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable core clock\n");

		goto err_clk_axi_m;

	}



	ret = clk_prepare_enable(res->axi_s_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable axi slave clock\n");

		goto err_clk_axi_s;

	}



	ret = clk_prepare_enable(res->ahb_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable ahb clock\n");

		goto err_clk_ahb;

	}



	ret = clk_prepare_enable(res->aux_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable aux clock\n");

		goto err_clk_aux;

	}



	writel(SLV_ADDR_SPACE_SZ,

		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);



	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);

	val &= ~BIT(0);

	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);



	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);



	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS

		| SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |

		AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,

		pcie->parf + PCIE20_PARF_SYS_CTRL);

	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);



	writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);

	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);

	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);



	val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);

	val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;

	writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);



	writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +

		PCIE20_DEVICE_CONTROL2_STATUS2);



	return 0;



err_clk_aux:

	clk_disable_unprepare(res->ahb_clk);

err_clk_ahb:

	clk_disable_unprepare(res->axi_s_clk);

err_clk_axi_s:

	clk_disable_unprepare(res->axi_m_clk);

err_clk_axi_m:

	clk_disable_unprepare(res->iface);

err_clk_iface:

	/*

	 * Not checking for failure, will anyway return

	 * the original failure in 'ret'.

	 */

	for (i = 0; i < ARRAY_SIZE(res->rst); i++)

		reset_control_assert(res->rst[i]);



	return ret;

}



static int qcom_pcie_link_up(struct dw_pcie *pci)

{

	u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
@@ -965,38 +1165,50 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 
	.rd_own_conf = qcom_pcie_rd_own_conf,

};



static const struct qcom_pcie_ops ops_v0 = {

	.get_resources = qcom_pcie_get_resources_v0,

	.init = qcom_pcie_init_v0,

	.deinit = qcom_pcie_deinit_v0,

	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,

/* Qcom IP rev.: 2.1.0	Synopsys IP rev.: 4.01a */

static const struct qcom_pcie_ops ops_2_1_0 = {

	.get_resources = qcom_pcie_get_resources_2_1_0,

	.init = qcom_pcie_init_2_1_0,

	.deinit = qcom_pcie_deinit_2_1_0,

	.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,

};



static const struct qcom_pcie_ops ops_v1 = {

	.get_resources = qcom_pcie_get_resources_v1,

	.init = qcom_pcie_init_v1,

	.deinit = qcom_pcie_deinit_v1,

	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,

/* Qcom IP rev.: 1.0.0	Synopsys IP rev.: 4.11a */

static const struct qcom_pcie_ops ops_1_0_0 = {

	.get_resources = qcom_pcie_get_resources_1_0_0,

	.init = qcom_pcie_init_1_0_0,

	.deinit = qcom_pcie_deinit_1_0_0,

	.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,

};



static const struct qcom_pcie_ops ops_v2 = {

	.get_resources = qcom_pcie_get_resources_v2,

	.init = qcom_pcie_init_v2,

	.post_init = qcom_pcie_post_init_v2,

	.deinit = qcom_pcie_deinit_v2,

	.post_deinit = qcom_pcie_post_deinit_v2,

	.ltssm_enable = qcom_pcie_v2_ltssm_enable,

/* Qcom IP rev.: 2.3.2	Synopsys IP rev.: 4.21a */

static const struct qcom_pcie_ops ops_2_3_2 = {

	.get_resources = qcom_pcie_get_resources_2_3_2,

	.init = qcom_pcie_init_2_3_2,

	.post_init = qcom_pcie_post_init_2_3_2,

	.deinit = qcom_pcie_deinit_2_3_2,

	.post_deinit = qcom_pcie_post_deinit_2_3_2,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

};



static const struct dw_pcie_ops dw_pcie_ops = {

	.link_up = qcom_pcie_link_up,

/* Qcom IP rev.: 2.4.0	Synopsys IP rev.: 4.20a */

static const struct qcom_pcie_ops ops_2_4_0 = {

	.get_resources = qcom_pcie_get_resources_2_4_0,

	.init = qcom_pcie_init_2_4_0,

	.deinit = qcom_pcie_deinit_2_4_0,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

};



/* Qcom IP rev.: 2.3.3	Synopsys IP rev.: 4.30a */

static const struct qcom_pcie_ops ops_2_3_3 = {

	.get_resources = qcom_pcie_get_resources_2_3_3,

	.init = qcom_pcie_init_2_3_3,

	.deinit = qcom_pcie_deinit_2_3_3,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

};



static const struct qcom_pcie_ops ops_v3 = {

	.get_resources = qcom_pcie_get_resources_v3,

	.init = qcom_pcie_init_v3,

	.deinit = qcom_pcie_deinit_v3,

	.ltssm_enable = qcom_pcie_v2_ltssm_enable,

static const struct dw_pcie_ops dw_pcie_ops = {

	.link_up = qcom_pcie_link_up,

};



static int qcom_pcie_probe(struct platform_device *pdev)
@@ -1085,11 +1297,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) 
}



static const struct of_device_id qcom_pcie_match[] = {

	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },

	{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },

	{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },

	{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },

	{ .compatible = "qcom,pcie-ipq4019", .data = &ops_v3 },

	{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },

	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },

	{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },

	{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },

	{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },

	{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },

	{ }

};