Commit cb9850d0 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I
Browse files

Merge branch 'next' into resolution 

Conflicts:
	drivers/extcon/extcon-adc-jack.c
	drivers/extcon/extcon-arizona.c
	drivers/extcon/extcon-gpio.c
	include/linux/extcon.h
parents 81522637 b78ea84a

Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt

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Driver for Broadcom Northstar USB 3.0 PHY



Required properties:



- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".

- reg: register mappings for DMP (Device Management Plugin) and ChipCommon B

       MMI.

- reg-names: "dmp" and "ccb-mii"



Initialization of USB 3.0 PHY depends on Northstar version. There are currently

three known series: Ax, Bx and Cx.

Known A0: BCM4707 rev 0

Known B0: BCM4707 rev 4, BCM53573 rev 2

Known B1: BCM4707 rev 6

Known C0: BCM47094 rev 0



Example:

	usb3-phy {

		compatible = "brcm,ns-ax-usb3-phy";

		reg = <0x18105000 0x1000>, <0x18003000 0x1000>;

		reg-names = "dmp", "ccb-mii";

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt

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ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK



Required properties (phy (parent) node):

 - compatible : should be one of the listed compatibles:

	* "rockchip,rk3366-usb2phy"

	* "rockchip,rk3399-usb2phy"

 - reg : the address offset of grf for usb-phy configuration.

 - #clock-cells : should be 0.

 - clock-output-names : specify the 480m output clock name.



Optional properties:

 - clocks : phandle + phy specifier pair, for the input clock of phy.

 - clock-names : input clock name of phy, must be "phyclk".



Required nodes : a sub-node is required for each port the phy provides.

		 The sub-node name is used to identify host or otg port,

		 and shall be the following entries:

	* "otg-port" : the name of otg port.

	* "host-port" : the name of host port.



Required properties (port (child) node):

 - #phy-cells : must be 0. See ./phy-bindings.txt for details.

 - interrupts : specify an interrupt for each entry in interrupt-names.

 - interrupt-names : a list which shall be the following entries:

	* "otg-id" : for the otg id interrupt.

	* "otg-bvalid" : for the otg vbus interrupt.

	* "linestate" : for the host/otg linestate interrupt.



Optional properties:

 - phy-supply : phandle to a regulator that provides power to VBUS.

		See ./phy-bindings.txt for details.



Example:



grf: syscon@ff770000 {

	compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";

	#address-cells = <1>;

	#size-cells = <1>;



...



	u2phy: usb2-phy@700 {

		compatible = "rockchip,rk3366-usb2phy";

		reg = <0x700 0x2c>;

		#clock-cells = <0>;

		clock-output-names = "sclk_otgphy0_480m";



		u2phy_otg: otg-port {

			#phy-cells = <0>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "otg-id", "otg-bvalid", "linestate";

			status = "okay";

		};



		u2phy_host: host-port {

			#phy-cells = <0>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "linestate";

			status = "okay";

		};

	};

};

Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt

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* ROCKCHIP type-c PHY

---------------------



Required properties:

 - compatible : must be "rockchip,rk3399-typec-phy"

 - reg: Address and length of the usb phy control register set

 - rockchip,grf : phandle to the syscon managing the "general

   register files"

 - clocks : phandle + clock specifier for the phy clocks

 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";

 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or

		    <&cru SCLK_UPHY1_TCPDCORE>;

 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000

 - resets : a list of phandle + reset specifier pairs

 - reset-names : string reset name, must be:

		 "uphy", "uphy-pipe", "uphy-tcphy"

 - extcon : extcon specifier for the Power Delivery



Note, there are 2 type-c phys for RK3399, and they are almost identical, except

these registers(description below), every register node contains 3 sections:

offset, enable bit, write mask bit.

 - rockchip,typec-conn-dir : the register of type-c connector direction,

   for type-c phy0, it must be <0xe580 0 16>;

   for type-c phy1, it must be <0xe58c 0 16>;

 - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable

   control.

   for type-c phy0, it must be <0xe580 3 19>;

   for type-c phy1, it must be <0xe58c 3 19>;

 - rockchip,external-psm : the register of type-c phy external psm clock

   selection.

   for type-c phy0, it must be <0xe588 14 30>;

   for type-c phy1, it must be <0xe594 14 30>;

 - rockchip,pipe-status : the register of type-c phy pipe status.

   for type-c phy0, it must be <0xe5c0 0 0>;

   for type-c phy1, it must be <0xe5c0 16 16>;



Required nodes : a sub-node is required for each port the phy provides.

		 The sub-node name is used to identify dp or usb3 port,

		 and shall be the following entries:

	* "dp-port" : the name of DP port.

	* "usb3-port" : the name of USB3 port.



Required properties (port (child) node):

- #phy-cells : must be 0, See ./phy-bindings.txt for details.



Example:

	tcphy0: phy@ff7c0000 {

		compatible = "rockchip,rk3399-typec-phy";

		reg = <0x0 0xff7c0000 0x0 0x40000>;

		rockchip,grf = <&grf>;

		extcon = <&fusb0>;

		clocks = <&cru SCLK_UPHY0_TCPDCORE>,

			 <&cru SCLK_UPHY0_TCPDPHY_REF>;

		clock-names = "tcpdcore", "tcpdphy-ref";

		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;

		assigned-clock-rates = <50000000>;

		resets = <&cru SRST_UPHY0>,

			 <&cru SRST_UPHY0_PIPE_L00>,

			 <&cru SRST_P_UPHY0_TCPHY>;

		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";

		rockchip,typec-conn-dir = <0xe580 0 16>;

		rockchip,usb3tousb2-en = <0xe580 3 19>;

		rockchip,external-psm = <0xe588 14 30>;

		rockchip,pipe-status = <0xe5c0 0 0>;



		tcphy0_dp: dp-port {

			#phy-cells = <0>;

		};



		tcphy0_usb3: usb3-port {

			#phy-cells = <0>;

		};

	};



	tcphy1: phy@ff800000 {

		compatible = "rockchip,rk3399-typec-phy";

		reg = <0x0 0xff800000 0x0 0x40000>;

		rockchip,grf = <&grf>;

		extcon = <&fusb1>;

		clocks = <&cru SCLK_UPHY1_TCPDCORE>,

			 <&cru SCLK_UPHY1_TCPDPHY_REF>;

		clock-names = "tcpdcore", "tcpdphy-ref";

		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;

		assigned-clock-rates = <50000000>;

		resets = <&cru SRST_UPHY1>,

			 <&cru SRST_UPHY1_PIPE_L00>,

			 <&cru SRST_P_UPHY1_TCPHY>;

		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";

		rockchip,typec-conn-dir = <0xe58c 0 16>;

		rockchip,usb3tousb2-en = <0xe58c 3 19>;

		rockchip,external-psm = <0xe594 14 30>;

		rockchip,pipe-status = <0xe5c0 16 16>;



		tcphy1_dp: dp-port {

			#phy-cells = <0>;

		};



		tcphy1_usb3: usb3-port {

			#phy-cells = <0>;

		};

	};

Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt

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@@ -5,6 +5,8 @@ This file provides information on what the device node for the R-Car generation 


Required properties:

- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

	      SoC.

	      "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796

	      SoC.

	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
@@ -30,11 +32,11 @@ Example (R-Car H3): 
		compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";

		reg = <0 0xee080200 0 0x700>;

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

		clocks = <&cpg CPG_MOD 703>;

	};



	usb-phy@ee0a0200 {

		compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";

		reg = <0 0xee0a0200 0 0x700>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

		clocks = <&cpg CPG_MOD 702>;

	};

Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

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Rockchip PCIE PHY

-----------------------



Required properties:

 - compatible: rockchip,rk3399-pcie-phy

 - #phy-cells: must be 0

 - clocks: Must contain an entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

 - clock-names: Must be "refclk"

 - resets: Must contain an entry in reset-names.

	See ../reset/reset.txt for details.

 - reset-names: Must be "phy"



Example:



grf: syscon@ff770000 {

	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";

	#address-cells = <1>;

	#size-cells = <1>;



	...



	pcie_phy: pcie-phy {

		compatible = "rockchip,rk3399-pcie-phy";

		#phy-cells = <0>;

		clocks = <&cru SCLK_PCIEPHY_REF>;

		clock-names = "refclk";

		resets = <&cru SRST_PCIEPHY>;

		reset-names = "phy";

	};

};