Commit cb807055 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Limit plane stride to below TILEOFF.x limit 



Limit pre-skl plane stride to below 4k or 8k pixels (depending on
the platform). We do this in order guarantee that TILEOFF/OFFSET.x
does not get too big.

Currently this is not a problem as we align SURF to 4k, and so
TILEOFF/OFFSET only have to deal with a single tile's worth of
pixels. But for async flips we're going to have to bump SURF
alignment to 256k, and thus we can no longer guarantee
TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid
this by borrowing a trick from the skl+ code and limit the max
plane stride to whatever value we can fit into TILEOFF/OFFSET.x.

The slight downside is that we may end up doing GTT remapping in
a few more cases where previously we did not have to. But since
that will only happen with huge buffers I'm not really concerned
about it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarKarthik B S <karthik.b.s@intel.com>
parent 66a24509

drivers/gpu/drm/i915/display/i9xx_plane.c

+55 −9
Original line number Diff line number Diff line
@@ -530,21 +530,56 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 
	return ret;

}



unsigned int

i9xx_plane_max_stride(struct intel_plane *plane,

static unsigned int

hsw_primary_max_stride(struct intel_plane *plane,

		       u32 pixel_format, u64 modifier,

		       unsigned int rotation)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */

	return min(8192 * cpp, 32 * 1024);

}



static unsigned int

ilk_primary_max_stride(struct intel_plane *plane,

		       u32 pixel_format, u64 modifier,

		       unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	if (!HAS_GMCH(dev_priv)) {

	/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */

	if (modifier == I915_FORMAT_MOD_X_TILED)

		return min(4096 * cpp, 32 * 1024);

	else

		return 32 * 1024;

	} else if (INTEL_GEN(dev_priv) >= 4) {

}



unsigned int

i965_plane_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */

	if (modifier == I915_FORMAT_MOD_X_TILED)

			return 16*1024;

		return min(4096 * cpp, 16 * 1024);

	else

		return 32 * 1024;

	} else if (INTEL_GEN(dev_priv) >= 3) {

}



static unsigned int

i9xx_plane_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);



	if (INTEL_GEN(dev_priv) >= 3) {

		if (modifier == I915_FORMAT_MOD_X_TILED)

			return 8*1024;

		else
@@ -656,7 +691,18 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	else

		plane->min_cdclk = i9xx_plane_min_cdclk;



	if (HAS_GMCH(dev_priv)) {

		if (INTEL_GEN(dev_priv) >= 4)

			plane->max_stride = i965_plane_max_stride;

		else

			plane->max_stride = i9xx_plane_max_stride;

	} else {

		if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))

			plane->max_stride = hsw_primary_max_stride;

		else

			plane->max_stride = ilk_primary_max_stride;

	}



	plane->update_plane = i9xx_update_plane;

	plane->disable_plane = i9xx_disable_plane;

	plane->get_hw_state = i9xx_plane_get_hw_state;

drivers/gpu/drm/i915/display/i9xx_plane.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ struct drm_i915_private; 
struct intel_plane;

struct intel_plane_state;



unsigned int i9xx_plane_max_stride(struct intel_plane *plane,

unsigned int i965_plane_max_stride(struct intel_plane *plane,

				   u32 pixel_format, u64 modifier,

				   unsigned int rotation);

int i9xx_check_plane_surface(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

+27 −6
Original line number Diff line number Diff line
@@ -1851,7 +1851,26 @@ g4x_sprite_max_stride(struct intel_plane *plane, 
		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

{

	return 16384;

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */

	if (modifier == I915_FORMAT_MOD_X_TILED)

		return min(4096 * cpp, 16 * 1024);

	else

		return 16 * 1024;

}



static unsigned int

hsw_sprite_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */

	return min(8192 * cpp, 16 * 1024);

}



static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
@@ -3408,11 +3427,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 
		return plane;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		plane->max_stride = i9xx_plane_max_stride;

		plane->update_plane = vlv_update_plane;

		plane->disable_plane = vlv_disable_plane;

		plane->get_hw_state = vlv_plane_get_hw_state;

		plane->check_plane = vlv_sprite_check;

		plane->max_stride = i965_plane_max_stride;

		plane->min_cdclk = vlv_plane_min_cdclk;



		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -3426,16 +3445,18 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		plane_funcs = &vlv_sprite_funcs;

	} else if (INTEL_GEN(dev_priv) >= 7) {

		plane->max_stride = g4x_sprite_max_stride;

		plane->update_plane = ivb_update_plane;

		plane->disable_plane = ivb_disable_plane;

		plane->get_hw_state = ivb_plane_get_hw_state;

		plane->check_plane = g4x_sprite_check;



		if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))

		if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {

			plane->max_stride = hsw_sprite_max_stride;

			plane->min_cdclk = hsw_plane_min_cdclk;

		else

		} else {

			plane->max_stride = g4x_sprite_max_stride;

			plane->min_cdclk = ivb_sprite_min_cdclk;

		}



		formats = snb_plane_formats;

		num_formats = ARRAY_SIZE(snb_plane_formats);
@@ -3443,11 +3464,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		plane_funcs = &snb_sprite_funcs;

	} else {

		plane->max_stride = g4x_sprite_max_stride;

		plane->update_plane = g4x_update_plane;

		plane->disable_plane = g4x_disable_plane;

		plane->get_hw_state = g4x_plane_get_hw_state;

		plane->check_plane = g4x_sprite_check;

		plane->max_stride = g4x_sprite_max_stride;

		plane->min_cdclk = g4x_sprite_min_cdclk;



		modifiers = i9xx_plane_format_modifiers;