Commit cb7f49a3 authored by Samuel Holland's avatar Samuel Holland Committed by Vinod Koul
Browse files

phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last 



The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.

Reviewed-by: default avatarPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221114022113.31694-7-samuel@sholland.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a709ae51

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

+4 −4
Original line number Diff line number Diff line
@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) 
		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |

		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));



	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,

		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |

		     SUN6I_DPHY_GCTL_EN);



	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,

		     SUN6I_DPHY_ANA0_REG_PWS |

		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) 
			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,

			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));



	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,

		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |

		     SUN6I_DPHY_GCTL_EN);



	return 0;

}