Commit cb7cbaae authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2022-03-25' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Some fixes were queued up in and in light of the fbdev regressions,
  I've pulled those in as well.

  core:
   - Make audio and color plane support checking only happen when a CEA
     extension block is found.
   - Small selftest fix.

  fbdev:
   - two regressions fixes from speedup patches.

  ttm:
   - Fix a small regression from ttm_resource_fini()

  i915:
   - Reject unsupported TMDS rates on ICL+
   - Treat SAGV block time 0 as SAGV disabled
   - Fix PSF GV point mask when SAGV is not possible
   - Fix renamed INTEL_INFO->media.arch/ver field"

* tag 'drm-next-2022-03-25' of git://anongit.freedesktop.org/drm/drm:
  fbdev: Fix cfb_imageblit() for arbitrary image widths
  fbdev: Fix sys_imageblit() for arbitrary image widths
  drm/edid: fix CEA extension byte #3 parsing
  drm/edid: check basic audio support on CEA extension block
  drm/i915: Fix renamed struct field
  drm/i915: Fix PSF GV point mask when SAGV is not possible
  drm/i915: Treat SAGV block time 0 as SAGV disabled
  drm/i915: Reject unsupported TMDS rates on ICL+
  drm/selftest: plane_helper: Put test structures in static storage
  drm/ttm: Fix a kernel oops due to an invalid read
parents 46f538bf 2a81dba4

drivers/gpu/drm/drm_edid.c

+10 −5
Original line number Diff line number Diff line
@@ -4859,7 +4859,8 @@ bool drm_detect_monitor_audio(struct edid *edid) 
	if (!edid_ext)

		goto end;



	has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);

	has_audio = (edid_ext[0] == CEA_EXT &&

		    (edid_ext[3] & EDID_BASIC_AUDIO) != 0);



	if (has_audio) {

		DRM_DEBUG_KMS("Monitor has basic audio support\n");
@@ -5187,10 +5188,14 @@ static void drm_parse_cea_ext(struct drm_connector *connector, 


	/* The existence of a CEA block should imply RGB support */

	info->color_formats = DRM_COLOR_FORMAT_RGB444;



	/* CTA DisplayID Data Block does not have byte #3 */

	if (edid_ext[0] == CEA_EXT) {

		if (edid_ext[3] & EDID_CEA_YCRCB444)

			info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;

		if (edid_ext[3] & EDID_CEA_YCRCB422)

			info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;

	}



	if (cea_db_offsets(edid_ext, &start, &end))

		return;

drivers/gpu/drm/i915/display/intel_bw.c

+2 −1
Original line number Diff line number Diff line
@@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) 
	 * cause.

	 */

	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {

		allowed_points = BIT(max_bw_point);

		allowed_points &= ADLS_PSF_PT_MASK;

		allowed_points |= BIT(max_bw_point);

		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",

			    max_bw_point);

	}

drivers/gpu/drm/i915/display/intel_hdmi.c

+9 −0
Original line number Diff line number Diff line
@@ -1836,6 +1836,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, 
		      bool has_hdmi_sink)

{

	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);

	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);



	if (clock < 25000)

		return MODE_CLOCK_LOW;
@@ -1856,6 +1857,14 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, 
	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)

		return MODE_CLOCK_RANGE;



	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */

	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)

		return MODE_CLOCK_RANGE;



	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */

	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)

		return MODE_CLOCK_RANGE;



	/*

	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed

	 * set of link rates.

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -947,7 +947,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) 
	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))



#define MEDIA_VER(i915)			(INTEL_INFO(i915)->media.ver)

#define MEDIA_VER_FULL(i915)		IP_VER(INTEL_INFO(i915)->media.arch, \

#define MEDIA_VER_FULL(i915)		IP_VER(INTEL_INFO(i915)->media.ver, \

					       INTEL_INFO(i915)->media.rel)

#define IS_MEDIA_VER(i915, from, until) \

	(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))

drivers/gpu/drm/i915/intel_pm.c

+6 −4
Original line number Diff line number Diff line
@@ -3698,8 +3698,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) 
		MISSING_CASE(DISPLAY_VER(dev_priv));

	}



	/* Default to an unusable block time */

	dev_priv->sagv_block_time_us = -1;

	dev_priv->sagv_block_time_us = 0;

}



/*
@@ -5645,7 +5644,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 
	result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;

	result->enable = true;



	if (DISPLAY_VER(dev_priv) < 12)

	if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)

		result->can_sagv = latency >= dev_priv->sagv_block_time_us;

}
@@ -5678,7 +5677,10 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;

	struct skl_wm_level *levels = plane_wm->wm;

	unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;

	unsigned int latency = 0;



	if (dev_priv->sagv_block_time_us)

		latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];



	skl_compute_plane_wm(crtc_state, plane, 0, latency,

			     wm_params, &levels[0],