Commit cb6846fb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.17-2021-12-30' of ssh://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-5.17-2021-12-30:

amdgpu:
- Suspend/resume fixes
- Fence fix
- Misc code cleanups
- IP discovery fixes
- SRIOV fixes
- RAS fixes
- GMC 8 VRAM detection fix
- FRU fixes for Aldebaran
- Display fixes

amdkfd:
- SVM fixes
- IP discovery fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211230141032.613596-1-alexander.deucher@amd.com
parents 011e8c32 0637d417

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −1
Original line number Diff line number Diff line
@@ -812,6 +812,7 @@ struct amd_powerplay { 


#define AMDGPU_RESET_MAGIC_NUM 64

#define AMDGPU_MAX_DF_PERFMONS 4

#define AMDGPU_PRODUCT_NAME_LEN 64

struct amdgpu_device {

	struct device			*dev;

	struct pci_dev			*pdev;
@@ -1082,7 +1083,7 @@ struct amdgpu_device { 


	/* Chip product information */

	char				product_number[16];

	char				product_name[32];

	char				product_name[AMDGPU_PRODUCT_NAME_LEN];

	char				serial[20];



	atomic_t			throttling_logging_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+3 −3
Original line number Diff line number Diff line
@@ -721,13 +721,13 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 
	return adev->have_atomics_support;

}



void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev)

void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)

{

	struct ras_err_data err_data = {0, 0, 0, NULL};



	/* CPU MCA will handle page retirement if connected_to_cpu is 1 */

	if (!adev->gmc.xgmi.connected_to_cpu)

		amdgpu_umc_process_ras_data_cb(adev, &err_data, NULL);

	else

		amdgpu_umc_poison_handler(adev, &err_data, reset);

	else if (reset)

		amdgpu_amdkfd_gpu_reset(adev);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+2 −1
Original line number Diff line number Diff line
@@ -296,7 +296,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 
				      uint64_t *mmap_offset);

int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,

				struct tile_config *config);

void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev);

void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,

				bool reset);

#if IS_ENABLED(CONFIG_HSA_AMD)

void amdgpu_amdkfd_gpuvm_init_mem_limits(void);

void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+13 −14
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id) 


	lock_srbm(adev, mec, pipe, 0, 0);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),

	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,

		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
@@ -279,7 +279,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, 
		       lower_32_bits((uintptr_t)wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

		       upper_32_bits((uintptr_t)wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,

		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));

	}
@@ -488,13 +488,13 @@ bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev, 
	uint32_t low, high;



	acquire_queue(adev, pipe_id, queue_id);

	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

	if (act) {

		low = lower_32_bits(queue_address >> 8);

		high = upper_32_bits(queue_address >> 8);



		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&

		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))

		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

			retval = true;

	}

	release_queue(adev);
@@ -556,7 +556,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, 


	end_jiffies = (utimeout * HZ / 1000) + jiffies;

	while (true) {

		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))

			break;

		if (time_after(jiffies, end_jiffies)) {
@@ -645,7 +645,7 @@ int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev, 
	mutex_lock(&adev->grbm_idx_mutex);



	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);

	WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);



	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

		INSTANCE_BROADCAST_WRITES, 1);
@@ -722,7 +722,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, 
	pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;

	queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;

	soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);

	reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +

	reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +

			 queue_slot);

	*wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;

	if (*wave_cnt != 0)
@@ -809,8 +809,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
		for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {



			gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);

			queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,

					   mmSPI_CSQ_WF_ACTIVE_STATUS));

			queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);



			/*

			 * Assumption: queue map encodes following schema: four
@@ -860,17 +859,17 @@ void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, 
	/*

	 * Program TBA registers

	 */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),

	WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO,

                        lower_32_bits(tba_addr >> 8));

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),

	WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI,

                        upper_32_bits(tba_addr >> 8));



	/*

	 * Program TMA registers

	 */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),

	WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO,

			lower_32_bits(tma_addr >> 8));

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),

	WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_HI,

			upper_32_bits(tma_addr >> 8));



	unlock_srbm(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+29 −17
Original line number Diff line number Diff line
@@ -2317,6 +2317,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 


		/* need to do gmc hw init early so we can allocate gpu mem */

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			/* Try to reserve bad pages early */

			if (amdgpu_sriov_vf(adev))

				amdgpu_virt_exchange_data(adev);



			r = amdgpu_device_vram_scratch_init(adev);

			if (r) {

				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
@@ -2348,7 +2352,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
	}



	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_init_data_exchange(adev);

		amdgpu_virt_exchange_data(adev);



	r = amdgpu_ib_pool_init(adev);

	if (r) {
@@ -2615,11 +2619,10 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 
	if (r)

		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);



	/* For XGMI + passthrough configuration on arcturus, enable light SBR */

	if (adev->asic_type == CHIP_ARCTURUS &&

	    amdgpu_passthrough(adev) &&

	    adev->gmc.xgmi.num_physical_nodes > 1)

		smu_set_light_sbr(&adev->smu, true);

	/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */

	if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||

			       adev->asic_type == CHIP_ALDEBARAN ))

		smu_handle_passthrough_sbr(&adev->smu, true);



	if (adev->gmc.xgmi.num_physical_nodes > 1) {

		mutex_lock(&mgpu_info.mutex);
@@ -3182,6 +3185,12 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) 
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)

{

	switch (asic_type) {

#ifdef CONFIG_DRM_AMDGPU_SI

	case CHIP_HAINAN:

#endif

	case CHIP_TOPAZ:

		/* chips with no display hardware */

		return false;

#if defined(CONFIG_DRM_AMD_DC)

	case CHIP_TAHITI:

	case CHIP_PITCAIRN:
@@ -3573,6 +3582,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	if (r)

		return r;



	/* Need to get xgmi info early to decide the reset behavior*/

	if (adev->gmc.xgmi.supported) {

		r = adev->gfxhub.funcs->get_xgmi_info(adev);

		if (r)

			return r;

	}



	/* enable PCIE atomic ops */

	if (amdgpu_sriov_vf(adev))

		adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
@@ -3885,11 +3901,14 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) 


	amdgpu_irq_fini_hw(adev);



	if (adev->mman.initialized)

		ttm_device_clear_dma_mappings(&adev->mman.bdev);



	amdgpu_gart_dummy_page_fini(adev);



	if (drm_dev_is_unplugged(adev_to_drm(adev)))

		amdgpu_device_unmap_mmio(adev);



}



void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -4507,7 +4526,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) 
int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,

				 struct amdgpu_reset_context *reset_context)

{

	int i, j, r = 0;

	int i, r = 0;

	struct amdgpu_job *job = NULL;

	bool need_full_reset =

		test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
@@ -4529,15 +4548,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 


		/*clear job fence from fence drv to avoid force_completion

		 *leave NULL and vm flush fence in fence drv */

		for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {

			struct dma_fence *old, **ptr;

		amdgpu_fence_driver_clear_job_fences(ring);



			ptr = &ring->fence_drv.fences[j];

			old = rcu_dereference_protected(*ptr, 1);

			if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {

				RCU_INIT_POINTER(*ptr, NULL);

			}

		}

		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */

		amdgpu_fence_driver_force_completion(ring);

	}