Unverified Commit cb64fb0d authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!14262 x86/apic: Always explicitly disarm TSC-deadline timer 

Merge Pull Request from: @ci-robot 
 
PR sync from: Heyuan Wang <wangheyuan2@h-partners.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/PZAA6J5XSTRMFWLSSQYIJC2HMOYNICTT/ 
 
https://gitee.com/openeuler/kernel/issues/IBBN6V 
 
Link:https://gitee.com/openeuler/kernel/pulls/14262

 

Reviewed-by: default avatarYuan Can <yuancan@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: default avatarYuan Can <yuancan@huawei.com>
parents 5a23f5b9 11c79b45

arch/x86/kernel/apic/apic.c

+13 −1
Original line number Diff line number Diff line
@@ -488,7 +488,19 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) 
	v = apic_read(APIC_LVTT);

	v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);

	apic_write(APIC_LVTT, v);



	/*

	 * Setting APIC_LVT_MASKED (above) should be enough to tell

	 * the hardware that this timer will never fire. But AMD

	 * erratum 411 and some Intel CPU behavior circa 2024 say

	 * otherwise.  Time for belt and suspenders programming: mask

	 * the timer _and_ zero the counter registers:

	 */

	if (v & APIC_LVT_TIMER_TSCDEADLINE)

		wrmsrl(MSR_IA32_TSC_DEADLINE, 0);

	else

		apic_write(APIC_TMICT, 0);



	return 0;

}