Commit cb435fa6 authored by Atte Tommiska's avatar Atte Tommiska Committed by Herbert Xu
Browse files

hwrng: xiphera-trng: add support for XIP8001B hwrng 



Xiphera XIP8001B is an FPGA-based True Random Number Generator
Intellectual Property (IP) Core which can be instantiated in
multiple FPGA families. This driver adds Linux support for it through
the hwrng interface.

Signed-off-by: default avatarAtte Tommiska <atte.tommiska@xiphera.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 5c8c36e7

drivers/char/hw_random/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -512,6 +512,16 @@ config HW_RANDOM_CCTRNG 
	  will be called cctrng.

	  If unsure, say 'N'.



config HW_RANDOM_XIPHERA

	tristate "Xiphera FPGA based True Random Number Generator support"

	depends on HAS_IOMEM

	help

	  This driver provides kernel-side support for Xiphera True Random

	  Number Generator Intellectual Property Core.



	  To compile this driver as a module, choose M here: the

	  module will be called xiphera-trng.



endif # HW_RANDOM



config UML_RANDOM

drivers/char/hw_random/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -44,3 +44,4 @@ obj-$(CONFIG_HW_RANDOM_KEYSTONE) += ks-sa-rng.o 
obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-rng.o

obj-$(CONFIG_HW_RANDOM_NPCM) += npcm-rng.o

obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o

obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o

drivers/char/hw_random/xiphera-trng.c

0 → 100644
+150 −0
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// SPDX-License-Identifier: GPL-2.0

/* Copyright (C) 2020 Xiphera Ltd. */



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/hw_random.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/delay.h>



#define CONTROL_REG			0x00000000

#define STATUS_REG			0x00000004

#define RAND_REG			0x00000000



#define HOST_TO_TRNG_RESET		0x00000001

#define HOST_TO_TRNG_RELEASE_RESET	0x00000002

#define HOST_TO_TRNG_ENABLE		0x80000000

#define HOST_TO_TRNG_ZEROIZE		0x80000004

#define HOST_TO_TRNG_ACK_ZEROIZE	0x80000008

#define HOST_TO_TRNG_READ		0x8000000F



/* trng statuses */

#define TRNG_ACK_RESET			0x000000AC

#define TRNG_SUCCESSFUL_STARTUP		0x00000057

#define TRNG_FAILED_STARTUP		0x000000FA

#define TRNG_NEW_RAND_AVAILABLE		0x000000ED



struct xiphera_trng {

	void __iomem *mem;

	struct hwrng rng;

};



static int xiphera_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)

{

	struct xiphera_trng *trng = container_of(rng, struct xiphera_trng, rng);

	int ret = 0;



	while (max >= sizeof(u32)) {

		/* check for data */

		if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) {

			*(u32 *)buf = readl(trng->mem + RAND_REG);

			/*

			 * Inform the trng of the read

			 * and re-enable it to produce a new random number

			 */

			writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG);

			writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);

			ret += sizeof(u32);

			buf += sizeof(u32);

			max -= sizeof(u32);

		} else {

			break;

		}

	}

	return ret;

}



static int xiphera_trng_probe(struct platform_device *pdev)

{

	int ret;

	struct xiphera_trng *trng;

	struct device *dev = &pdev->dev;

	struct resource *res;



	trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL);

	if (!trng)

		return -ENOMEM;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	trng->mem = devm_ioremap_resource(dev, res);

	if (IS_ERR(trng->mem))

		return PTR_ERR(trng->mem);



	/*

	 * the trng needs to be reset first which might not happen in time,

	 * hence we incorporate a small delay to ensure proper behaviour

	 */

	writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG);

	usleep_range(100, 200);



	if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {

		/*

		 * there is a small chance the trng is just not ready yet,

		 * so we try one more time. If the second time fails, we give up

		 */

		usleep_range(100, 200);

		if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {

			dev_err(dev, "failed to reset the trng ip\n");

			return -ENODEV;

		}

	}



	/*

	 * once again, to ensure proper behaviour we sleep

	 * for a while after zeroizing the trng

	 */

	writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG);

	writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);

	writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG);

	msleep(20);



	if (readl(trng->mem + STATUS_REG) != TRNG_SUCCESSFUL_STARTUP) {

		/* diagnose the reason for the failure */

		if (readl(trng->mem + STATUS_REG) == TRNG_FAILED_STARTUP) {

			dev_err(dev, "trng ip startup-tests failed\n");

			return -ENODEV;

		}

		dev_err(dev, "startup-tests yielded no response\n");

		return -ENODEV;

	}



	writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG);



	trng->rng.name = pdev->name;

	trng->rng.read = xiphera_trng_read;

	trng->rng.quality = 900;



	ret = devm_hwrng_register(dev, &trng->rng);

	if (ret) {

		dev_err(dev, "failed to register rng device: %d\n", ret);

		return ret;

	}



	platform_set_drvdata(pdev, trng);



	return 0;

}



static const struct of_device_id xiphera_trng_of_match[] = {

	{ .compatible = "xiphera,xip8001b-trng", },

	{},

};

MODULE_DEVICE_TABLE(of, xiphera_trng_of_match);



static struct platform_driver xiphera_trng_driver = {

	.driver = {

		.name = "xiphera-trng",

		.of_match_table	= xiphera_trng_of_match,

	},

	.probe = xiphera_trng_probe,

};



module_platform_driver(xiphera_trng_driver);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Atte Tommiska");

MODULE_DESCRIPTION("Xiphera FPGA-based true random number generator driver");