Commit cb3ac594 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Boyd
Browse files

clk: tegra: Refactor fractional divider calculation 



Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.

Signed-off-by: default avatarPeter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarAapo Vienamo <avienamo@nvidia.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0cbb61a3

drivers/clk/tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o 
obj-y					+= cvb.o

obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o

obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o

obj-y					+= clk-utils.o

drivers/clk/tegra/clk-divider.c

+5 −25
Original line number Diff line number Diff line
@@ -32,35 +32,15 @@ 
static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,

		   unsigned long parent_rate)

{

	u64 divider_ux1 = parent_rate;

	u8 flags = divider->flags;

	int mul;



	if (!rate)

		return 0;



	mul = get_mul(divider);



	if (!(flags & TEGRA_DIVIDER_INT))

		divider_ux1 *= mul;



	if (flags & TEGRA_DIVIDER_ROUND_UP)

		divider_ux1 += rate - 1;



	do_div(divider_ux1, rate);



	if (flags & TEGRA_DIVIDER_INT)

		divider_ux1 *= mul;

	int div;



	divider_ux1 -= mul;

	div = div_frac_get(rate, parent_rate, divider->width,

			   divider->frac_width, divider->flags);



	if ((s64)divider_ux1 < 0)

	if (div < 0)

		return 0;



	if (divider_ux1 > get_max_div(divider))

		return get_max_div(divider);



	return divider_ux1;

	return div;

}



static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,

drivers/clk/tegra/clk-utils.c

0 → 100644
+43 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.

 */



#include <asm/div64.h>



#include "clk.h"



#define div_mask(w) ((1 << (w)) - 1)



int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,

		 u8 frac_width, u8 flags)

{

	u64 divider_ux1 = parent_rate;

	int mul;



	if (!rate)

		return 0;



	mul = 1 << frac_width;



	if (!(flags & TEGRA_DIVIDER_INT))

		divider_ux1 *= mul;



	if (flags & TEGRA_DIVIDER_ROUND_UP)

		divider_ux1 += rate - 1;



	do_div(divider_ux1, rate);



	if (flags & TEGRA_DIVIDER_INT)

		divider_ux1 *= mul;



	if (divider_ux1 < mul)

		return 0;



	divider_ux1 -= mul;



	if (divider_ux1 > div_mask(width))

		return div_mask(width);



	return divider_ux1;

}

drivers/clk/tegra/clk.h

+3 −0
Original line number Diff line number Diff line
@@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);

u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);

int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);

int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,

		 u8 frac_width, u8 flags);





/* Combined read fence with delay */

#define fence_udelay(delay, reg)	\