Loading drivers/memory/tegra/mc.c +9 −9 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ static const struct of_device_id tegra_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); static int terga_mc_block_dma_common(struct tegra_mc *mc, static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -90,13 +90,13 @@ static int terga_mc_block_dma_common(struct tegra_mc *mc, return 0; } static bool terga_mc_dma_idling_common(struct tegra_mc *mc, static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; } static int terga_mc_unblock_dma_common(struct tegra_mc *mc, static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -112,17 +112,17 @@ static int terga_mc_unblock_dma_common(struct tegra_mc *mc, return 0; } static int terga_mc_reset_status_common(struct tegra_mc *mc, static int tegra_mc_reset_status_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; } const struct tegra_mc_reset_ops terga_mc_reset_ops_common = { .block_dma = terga_mc_block_dma_common, .dma_idling = terga_mc_dma_idling_common, .unblock_dma = terga_mc_unblock_dma_common, .reset_status = terga_mc_reset_status_common, const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { .block_dma = tegra_mc_block_dma_common, .dma_idling = tegra_mc_dma_idling_common, .unblock_dma = tegra_mc_unblock_dma_common, .reset_status = tegra_mc_reset_status_common, }; static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) Loading drivers/memory/tegra/mc.h +1 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ static inline void mc_writel(struct tegra_mc *mc, u32 value, writel_relaxed(value, mc->regs + offset); } extern const struct tegra_mc_reset_ops terga_mc_reset_ops_common; extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common; #ifdef CONFIG_ARCH_TEGRA_2x_SOC extern const struct tegra_mc_soc tegra20_mc_soc; Loading drivers/memory/tegra/tegra114.c +1 −1 Original line number Diff line number Diff line Loading @@ -975,7 +975,7 @@ const struct tegra_mc_soc tegra114_mc_soc = { .smmu = &tegra114_smmu_soc, .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra114_mc_resets, .num_resets = ARRAY_SIZE(tegra114_mc_resets), }; drivers/memory/tegra/tegra124.c +2 −2 Original line number Diff line number Diff line Loading @@ -1074,7 +1074,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), }; Loading Loading @@ -1104,7 +1104,7 @@ const struct tegra_mc_soc tegra132_mc_soc = { .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), }; Loading drivers/memory/tegra/tegra20.c +14 −14 Original line number Diff line number Diff line Loading @@ -198,7 +198,7 @@ static const struct tegra_mc_reset tegra20_mc_resets[] = { TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14), }; static int terga20_mc_hotreset_assert(struct tegra_mc *mc, static int tegra20_mc_hotreset_assert(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -214,7 +214,7 @@ static int terga20_mc_hotreset_assert(struct tegra_mc *mc, return 0; } static int terga20_mc_hotreset_deassert(struct tegra_mc *mc, static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -230,7 +230,7 @@ static int terga20_mc_hotreset_deassert(struct tegra_mc *mc, return 0; } static int terga20_mc_block_dma(struct tegra_mc *mc, static int tegra20_mc_block_dma(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -246,19 +246,19 @@ static int terga20_mc_block_dma(struct tegra_mc *mc, return 0; } static bool terga20_mc_dma_idling(struct tegra_mc *mc, static bool tegra20_mc_dma_idling(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return mc_readl(mc, rst->status) == 0; } static int terga20_mc_reset_status(struct tegra_mc *mc, static int tegra20_mc_reset_status(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; } static int terga20_mc_unblock_dma(struct tegra_mc *mc, static int tegra20_mc_unblock_dma(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -274,13 +274,13 @@ static int terga20_mc_unblock_dma(struct tegra_mc *mc, return 0; } static const struct tegra_mc_reset_ops terga20_mc_reset_ops = { .hotreset_assert = terga20_mc_hotreset_assert, .hotreset_deassert = terga20_mc_hotreset_deassert, .block_dma = terga20_mc_block_dma, .dma_idling = terga20_mc_dma_idling, .unblock_dma = terga20_mc_unblock_dma, .reset_status = terga20_mc_reset_status, static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .hotreset_assert = tegra20_mc_hotreset_assert, .hotreset_deassert = tegra20_mc_hotreset_deassert, .block_dma = tegra20_mc_block_dma, .dma_idling = tegra20_mc_dma_idling, .unblock_dma = tegra20_mc_unblock_dma, .reset_status = tegra20_mc_reset_status, }; const struct tegra_mc_soc tegra20_mc_soc = { Loading @@ -290,7 +290,7 @@ const struct tegra_mc_soc tegra20_mc_soc = { .client_id_mask = 0x3f, .intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE | MC_INT_DECERR_EMEM, .reset_ops = &terga20_mc_reset_ops, .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), }; Loading
drivers/memory/tegra/mc.c +9 −9 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ static const struct of_device_id tegra_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); static int terga_mc_block_dma_common(struct tegra_mc *mc, static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -90,13 +90,13 @@ static int terga_mc_block_dma_common(struct tegra_mc *mc, return 0; } static bool terga_mc_dma_idling_common(struct tegra_mc *mc, static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; } static int terga_mc_unblock_dma_common(struct tegra_mc *mc, static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -112,17 +112,17 @@ static int terga_mc_unblock_dma_common(struct tegra_mc *mc, return 0; } static int terga_mc_reset_status_common(struct tegra_mc *mc, static int tegra_mc_reset_status_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; } const struct tegra_mc_reset_ops terga_mc_reset_ops_common = { .block_dma = terga_mc_block_dma_common, .dma_idling = terga_mc_dma_idling_common, .unblock_dma = terga_mc_unblock_dma_common, .reset_status = terga_mc_reset_status_common, const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { .block_dma = tegra_mc_block_dma_common, .dma_idling = tegra_mc_dma_idling_common, .unblock_dma = tegra_mc_unblock_dma_common, .reset_status = tegra_mc_reset_status_common, }; static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) Loading
drivers/memory/tegra/mc.h +1 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ static inline void mc_writel(struct tegra_mc *mc, u32 value, writel_relaxed(value, mc->regs + offset); } extern const struct tegra_mc_reset_ops terga_mc_reset_ops_common; extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common; #ifdef CONFIG_ARCH_TEGRA_2x_SOC extern const struct tegra_mc_soc tegra20_mc_soc; Loading
drivers/memory/tegra/tegra114.c +1 −1 Original line number Diff line number Diff line Loading @@ -975,7 +975,7 @@ const struct tegra_mc_soc tegra114_mc_soc = { .smmu = &tegra114_smmu_soc, .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra114_mc_resets, .num_resets = ARRAY_SIZE(tegra114_mc_resets), };
drivers/memory/tegra/tegra124.c +2 −2 Original line number Diff line number Diff line Loading @@ -1074,7 +1074,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), }; Loading Loading @@ -1104,7 +1104,7 @@ const struct tegra_mc_soc tegra132_mc_soc = { .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .reset_ops = &terga_mc_reset_ops_common, .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), }; Loading
drivers/memory/tegra/tegra20.c +14 −14 Original line number Diff line number Diff line Loading @@ -198,7 +198,7 @@ static const struct tegra_mc_reset tegra20_mc_resets[] = { TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14), }; static int terga20_mc_hotreset_assert(struct tegra_mc *mc, static int tegra20_mc_hotreset_assert(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -214,7 +214,7 @@ static int terga20_mc_hotreset_assert(struct tegra_mc *mc, return 0; } static int terga20_mc_hotreset_deassert(struct tegra_mc *mc, static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -230,7 +230,7 @@ static int terga20_mc_hotreset_deassert(struct tegra_mc *mc, return 0; } static int terga20_mc_block_dma(struct tegra_mc *mc, static int tegra20_mc_block_dma(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -246,19 +246,19 @@ static int terga20_mc_block_dma(struct tegra_mc *mc, return 0; } static bool terga20_mc_dma_idling(struct tegra_mc *mc, static bool tegra20_mc_dma_idling(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return mc_readl(mc, rst->status) == 0; } static int terga20_mc_reset_status(struct tegra_mc *mc, static int tegra20_mc_reset_status(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; } static int terga20_mc_unblock_dma(struct tegra_mc *mc, static int tegra20_mc_unblock_dma(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; Loading @@ -274,13 +274,13 @@ static int terga20_mc_unblock_dma(struct tegra_mc *mc, return 0; } static const struct tegra_mc_reset_ops terga20_mc_reset_ops = { .hotreset_assert = terga20_mc_hotreset_assert, .hotreset_deassert = terga20_mc_hotreset_deassert, .block_dma = terga20_mc_block_dma, .dma_idling = terga20_mc_dma_idling, .unblock_dma = terga20_mc_unblock_dma, .reset_status = terga20_mc_reset_status, static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .hotreset_assert = tegra20_mc_hotreset_assert, .hotreset_deassert = tegra20_mc_hotreset_deassert, .block_dma = tegra20_mc_block_dma, .dma_idling = tegra20_mc_dma_idling, .unblock_dma = tegra20_mc_unblock_dma, .reset_status = tegra20_mc_reset_status, }; const struct tegra_mc_soc tegra20_mc_soc = { Loading @@ -290,7 +290,7 @@ const struct tegra_mc_soc tegra20_mc_soc = { .client_id_mask = 0x3f, .intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE | MC_INT_DECERR_EMEM, .reset_ops = &terga20_mc_reset_ops, .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), };