!3285 arm64: errata: add option to disable cache readunique prefetch on HIP08

Merge Pull Request from: @ci-robot 
 
PR sync from: Yang Yingliang <yangyingliang@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/OIBVUYEE63LJQN5A4IZ6V6FO7K7PJ77U/ 
Random performance decreases appear on cases of Hackbench which test
pipe or socket communication among multi-threads on Hisi HIP08 SoC.
Cache sharing which caused by the change of the data layout and the
cache readunique prefetch mechanism both lead to this problem.

Readunique mechanism which may caused by store operation will invalid
cachelines on other cores during data fetching stage which can cause
cacheline invalidation happens frequently in a sharing data access
situation.

Disable cache readunique prefetch can trackle this problem.
Test cases are like:
```
for i in 20;do
        echo "--------pipe thread num=$i----------"
        for j in $(seq 1 10);do
            ./hackbench -pipe $i thread 1000
        done
    done
```
We disable readunique prefetch only in el2 for in el1 disabling
readunique prefetch may cause panic due to lack of related priority
which often be set in BIOS.

Introduce CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH and disable RU
prefetch using boot cmdline 'readunique_prefetch=off'.

Kai Shen (1):
  arm64: errata: add option to disable cache readunique prefetch on
    HIP08

Xie XiuQi (1):
  arm64: errata: enable HISILICON_ERRATUM_HIP08_RU_PREFETCH


-- 
2.25.1
 
https://gitee.com/openeuler/kernel/issues/I8MKTT 
 
Link:https://gitee.com/openeuler/kernel/pulls/3285

 

Reviewed-by: Zhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Reviewed-by: Liu Chao <liuchao173@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>