Commit cae5cb0c authored by Jouni Högander's avatar Jouni Högander Committed by Ville Syrjälä
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drm/i915/psr: Disable PSR2 when SDP is sent on prior line 



Selective update doesn't work if SU start address is 0 and start/end
SDP is configured to be sent prior to SU start/end lines. PSR2 has to be
disabled in this case for Alder Lake.

HSDES: 22012279113

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220905102355.176622-3-jouni.hogander@intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent eccfba17

drivers/gpu/drm/i915/display/intel_psr.c

+2 −1
Original line number Diff line number Diff line
@@ -811,7 +811,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d 
	if ((hblank_ns - req_ns) > 100)

		return true;



	if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

	/* Not supported <13 / Wa_22012279113:adl-p */

	if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

		return false;



	crtc_state->req_psr2_sdp_prior_scanline = true;