Commit cadbb580 authored by Allen Pais's avatar Allen Pais Committed by David S. Miller
Browse files

sparc64: correctly recognise M6 and M7 cpu type 



The following patch adds support for correctly
recognising M6 and M7 cpu type.

Signed-off-by: default avatarAllen Pais <allen.pais@oracle.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 619df5d2

arch/sparc/include/asm/spitfire.h

+2 −0
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ 
#define SUN4V_CHIP_NIAGARA3	0x03

#define SUN4V_CHIP_NIAGARA4	0x04

#define SUN4V_CHIP_NIAGARA5	0x05

#define SUN4V_CHIP_SPARC_M6	0x06

#define SUN4V_CHIP_SPARC_M7	0x07

#define SUN4V_CHIP_SPARC64X	0x8a

#define SUN4V_CHIP_UNKNOWN	0xff

arch/sparc/kernel/cpu.c

+12 −0
Original line number Diff line number Diff line
@@ -494,6 +494,18 @@ static void __init sun4v_cpu_probe(void) 
		sparc_pmu_type = "niagara5";

		break;



	case SUN4V_CHIP_SPARC_M6:

		sparc_cpu_type = "SPARC-M6";

		sparc_fpu_type = "SPARC-M6 integrated FPU";

		sparc_pmu_type = "sparc-m6";

		break;



	case SUN4V_CHIP_SPARC_M7:

		sparc_cpu_type = "SPARC-M7";

		sparc_fpu_type = "SPARC-M7 integrated FPU";

		sparc_pmu_type = "sparc-m7";

		break;



	case SUN4V_CHIP_SPARC64X:

		sparc_cpu_type = "SPARC64-X";

		sparc_fpu_type = "SPARC64-X integrated FPU";

arch/sparc/kernel/head_64.S

+12 −0
Original line number Diff line number Diff line
@@ -427,6 +427,12 @@ sun4v_chip_type: 
	cmp	%g2, '5'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA5, %g4

	cmp	%g2, '6'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_M6, %g4

	cmp	%g2, '7'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_SPARC_M7, %g4

	ba,pt	%xcc, 49f

	 nop
@@ -583,6 +589,12 @@ niagara_tlb_fixup: 
	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_NIAGARA5

	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_SPARC_M6

	be,pt	%xcc, niagara4_patch

	 nop

	cmp	%g1, SUN4V_CHIP_SPARC_M7

	be,pt	%xcc, niagara4_patch

	 nop