Loading Documentation/kernel-parameters.txt +1 −10 Original line number Diff line number Diff line Loading @@ -1039,16 +1039,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Claim all unknown PCI IDE storage controllers. idle= [X86] Format: idle=poll, idle=mwait, idle=halt, idle=nomwait Format: idle=poll, idle=halt, idle=nomwait Poll forces a polling idle loop that can slightly improve the performance of waking up a idle CPU, but will use a lot of power and make the system run hot. Not recommended. idle=mwait: On systems which support MONITOR/MWAIT but the kernel chose to not use it because it doesn't save as much power as a normal idle loop, use the MONITOR/MWAIT idle loop anyways. Performance should be the same as idle=poll. idle=halt: Halt is forced to be used for CPU idle. In such case C2/C3 won't be used again. idle=nomwait: Disable mwait for CPU C-states Loading Loading @@ -1886,10 +1881,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. wfi(ARM) instruction doesn't work correctly and not to use it. This is also useful when using JTAG debugger. no-hlt [BUGS=X86-32] Tells the kernel that the hlt instruction doesn't work correctly and not to use it. no_file_caps Tells the kernel not to honor file capabilities. The only way then for a file to be executed with privilege is to be setuid root or executed by root. Loading arch/x86/include/asm/processor.h +6 −12 Original line number Diff line number Diff line Loading @@ -89,7 +89,6 @@ struct cpuinfo_x86 { char wp_works_ok; /* It doesn't on 386's */ /* Problems on some 486Dx4's and old 386's: */ char hlt_works_ok; char hard_math; char rfu; char fdiv_bug; Loading Loading @@ -165,15 +164,6 @@ DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); extern const struct seq_operations cpuinfo_op; static inline int hlt_works(int cpu) { #ifdef CONFIG_X86_32 return cpu_data(cpu).hlt_works_ok; #else return 1; #endif } #define cache_line_size() (boot_cpu_data.x86_cache_alignment) extern void cpu_detect(struct cpuinfo_x86 *c); Loading Loading @@ -725,7 +715,7 @@ extern unsigned long boot_option_idle_override; extern bool amd_e400_c1e_detected; enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, IDLE_POLL, IDLE_FORCE_MWAIT}; IDLE_POLL}; extern void enable_sep_cpu(void); extern int sysenter_setup(void); Loading Loading @@ -998,7 +988,11 @@ extern unsigned long arch_align_stack(unsigned long sp); extern void free_init_pages(char *what, unsigned long begin, unsigned long end); void default_idle(void); bool set_pm_idle_to_default(void); #ifdef CONFIG_XEN bool xen_set_default_idle(void); #else #define xen_set_default_idle 0 #endif void stop_this_cpu(void *dummy); Loading arch/x86/kernel/cpu/bugs.c +0 −27 Original line number Diff line number Diff line Loading @@ -17,15 +17,6 @@ #include <asm/paravirt.h> #include <asm/alternative.h> static int __init no_halt(char *s) { WARN_ONCE(1, "\"no-hlt\" is deprecated, please use \"idle=poll\"\n"); boot_cpu_data.hlt_works_ok = 0; return 1; } __setup("no-hlt", no_halt); static int __init no_387(char *s) { boot_cpu_data.hard_math = 0; Loading Loading @@ -89,23 +80,6 @@ static void __init check_fpu(void) pr_warn("Hmm, FPU with FDIV bug\n"); } static void __init check_hlt(void) { if (boot_cpu_data.x86 >= 5 || paravirt_enabled()) return; pr_info("Checking 'hlt' instruction... "); if (!boot_cpu_data.hlt_works_ok) { pr_cont("disabled\n"); return; } halt(); halt(); halt(); halt(); pr_cont("OK\n"); } /* * Check whether we are able to run this kernel safely on SMP. * Loading @@ -129,7 +103,6 @@ void __init check_bugs(void) print_cpu_info(&boot_cpu_data); #endif check_config(); check_hlt(); init_utsname()->machine[1] = '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); alternative_instructions(); Loading arch/x86/kernel/cpu/proc.c +0 −2 Original line number Diff line number Diff line Loading @@ -28,7 +28,6 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c) { seq_printf(m, "fdiv_bug\t: %s\n" "hlt_bug\t\t: %s\n" "f00f_bug\t: %s\n" "coma_bug\t: %s\n" "fpu\t\t: %s\n" Loading @@ -36,7 +35,6 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c) "cpuid level\t: %d\n" "wp\t\t: %s\n", c->fdiv_bug ? "yes" : "no", c->hlt_works_ok ? "no" : "yes", c->f00f_bug ? "yes" : "no", c->coma_bug ? "yes" : "no", c->hard_math ? "yes" : "no", Loading arch/x86/kernel/process.c +6 −83 Original line number Diff line number Diff line Loading @@ -390,7 +390,8 @@ void default_idle(void) EXPORT_SYMBOL(default_idle); #endif bool set_pm_idle_to_default(void) #ifdef CONFIG_XEN bool xen_set_default_idle(void) { bool ret = !!x86_idle; Loading @@ -398,6 +399,7 @@ bool set_pm_idle_to_default(void) return ret; } #endif void stop_this_cpu(void *dummy) { local_irq_disable(); Loading @@ -407,32 +409,9 @@ void stop_this_cpu(void *dummy) set_cpu_online(smp_processor_id(), false); disable_local_APIC(); for (;;) { if (hlt_works(smp_processor_id())) for (;;) halt(); } } /* Default MONITOR/MWAIT with no hints, used for default C1 state */ static void mwait_idle(void) { if (!need_resched()) { trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle_rcuidle(1, smp_processor_id()); if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) clflush((void *)¤t_thread_info()->flags); __monitor((void *)¤t_thread_info()->flags, 0, 0); smp_mb(); if (!need_resched()) __sti_mwait(0, 0); else local_irq_enable(); trace_power_end_rcuidle(smp_processor_id()); trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); } else local_irq_enable(); } /* * On SMP it's slightly faster (but much more power-consuming!) Loading @@ -450,53 +429,6 @@ static void poll_idle(void) trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); } /* * mwait selection logic: * * It depends on the CPU. For AMD CPUs that support MWAIT this is * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings * then depend on a clock divisor and current Pstate of the core. If * all cores of a processor are in halt state (C1) the processor can * enter the C1E (C1 enhanced) state. If mwait is used this will never * happen. * * idle=mwait overrides this decision and forces the usage of mwait. */ #define MWAIT_INFO 0x05 #define MWAIT_ECX_EXTENDED_INFO 0x01 #define MWAIT_EDX_C1 0xf0 int mwait_usable(const struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; /* Use mwait if idle=mwait boot option is given */ if (boot_option_idle_override == IDLE_FORCE_MWAIT) return 1; /* * Any idle= boot option other than idle=mwait means that we must not * use mwait. Eg: idle=halt or idle=poll or idle=nomwait */ if (boot_option_idle_override != IDLE_NO_OVERRIDE) return 0; if (c->cpuid_level < MWAIT_INFO) return 0; cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); /* Check, whether EDX has extended info about MWAIT */ if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) return 1; /* * edx enumeratios MONITOR/MWAIT extensions. Check, whether * C1 supports MWAIT */ return (edx & MWAIT_EDX_C1); } bool amd_e400_c1e_detected; EXPORT_SYMBOL(amd_e400_c1e_detected); Loading Loading @@ -567,13 +499,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) if (x86_idle) return; if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { /* * One CPU supports mwait => All CPUs supports mwait */ pr_info("using mwait in idle threads\n"); x86_idle = mwait_idle; } else if (cpu_has_amd_erratum(amd_erratum_400)) { if (cpu_has_amd_erratum(amd_erratum_400)) { /* E400: APIC timer interrupt does not wake up CPU from C1e */ pr_info("using AMD E400 aware idle routine\n"); x86_idle = amd_e400_idle; Loading @@ -597,9 +523,6 @@ static int __init idle_setup(char *str) pr_info("using polling idle threads\n"); x86_idle = poll_idle; boot_option_idle_override = IDLE_POLL; } else if (!strcmp(str, "mwait")) { boot_option_idle_override = IDLE_FORCE_MWAIT; WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); } else if (!strcmp(str, "halt")) { /* * When the boot option of idle=halt is added, halt is Loading Loading
Documentation/kernel-parameters.txt +1 −10 Original line number Diff line number Diff line Loading @@ -1039,16 +1039,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Claim all unknown PCI IDE storage controllers. idle= [X86] Format: idle=poll, idle=mwait, idle=halt, idle=nomwait Format: idle=poll, idle=halt, idle=nomwait Poll forces a polling idle loop that can slightly improve the performance of waking up a idle CPU, but will use a lot of power and make the system run hot. Not recommended. idle=mwait: On systems which support MONITOR/MWAIT but the kernel chose to not use it because it doesn't save as much power as a normal idle loop, use the MONITOR/MWAIT idle loop anyways. Performance should be the same as idle=poll. idle=halt: Halt is forced to be used for CPU idle. In such case C2/C3 won't be used again. idle=nomwait: Disable mwait for CPU C-states Loading Loading @@ -1886,10 +1881,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. wfi(ARM) instruction doesn't work correctly and not to use it. This is also useful when using JTAG debugger. no-hlt [BUGS=X86-32] Tells the kernel that the hlt instruction doesn't work correctly and not to use it. no_file_caps Tells the kernel not to honor file capabilities. The only way then for a file to be executed with privilege is to be setuid root or executed by root. Loading
arch/x86/include/asm/processor.h +6 −12 Original line number Diff line number Diff line Loading @@ -89,7 +89,6 @@ struct cpuinfo_x86 { char wp_works_ok; /* It doesn't on 386's */ /* Problems on some 486Dx4's and old 386's: */ char hlt_works_ok; char hard_math; char rfu; char fdiv_bug; Loading Loading @@ -165,15 +164,6 @@ DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); extern const struct seq_operations cpuinfo_op; static inline int hlt_works(int cpu) { #ifdef CONFIG_X86_32 return cpu_data(cpu).hlt_works_ok; #else return 1; #endif } #define cache_line_size() (boot_cpu_data.x86_cache_alignment) extern void cpu_detect(struct cpuinfo_x86 *c); Loading Loading @@ -725,7 +715,7 @@ extern unsigned long boot_option_idle_override; extern bool amd_e400_c1e_detected; enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, IDLE_POLL, IDLE_FORCE_MWAIT}; IDLE_POLL}; extern void enable_sep_cpu(void); extern int sysenter_setup(void); Loading Loading @@ -998,7 +988,11 @@ extern unsigned long arch_align_stack(unsigned long sp); extern void free_init_pages(char *what, unsigned long begin, unsigned long end); void default_idle(void); bool set_pm_idle_to_default(void); #ifdef CONFIG_XEN bool xen_set_default_idle(void); #else #define xen_set_default_idle 0 #endif void stop_this_cpu(void *dummy); Loading
arch/x86/kernel/cpu/bugs.c +0 −27 Original line number Diff line number Diff line Loading @@ -17,15 +17,6 @@ #include <asm/paravirt.h> #include <asm/alternative.h> static int __init no_halt(char *s) { WARN_ONCE(1, "\"no-hlt\" is deprecated, please use \"idle=poll\"\n"); boot_cpu_data.hlt_works_ok = 0; return 1; } __setup("no-hlt", no_halt); static int __init no_387(char *s) { boot_cpu_data.hard_math = 0; Loading Loading @@ -89,23 +80,6 @@ static void __init check_fpu(void) pr_warn("Hmm, FPU with FDIV bug\n"); } static void __init check_hlt(void) { if (boot_cpu_data.x86 >= 5 || paravirt_enabled()) return; pr_info("Checking 'hlt' instruction... "); if (!boot_cpu_data.hlt_works_ok) { pr_cont("disabled\n"); return; } halt(); halt(); halt(); halt(); pr_cont("OK\n"); } /* * Check whether we are able to run this kernel safely on SMP. * Loading @@ -129,7 +103,6 @@ void __init check_bugs(void) print_cpu_info(&boot_cpu_data); #endif check_config(); check_hlt(); init_utsname()->machine[1] = '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); alternative_instructions(); Loading
arch/x86/kernel/cpu/proc.c +0 −2 Original line number Diff line number Diff line Loading @@ -28,7 +28,6 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c) { seq_printf(m, "fdiv_bug\t: %s\n" "hlt_bug\t\t: %s\n" "f00f_bug\t: %s\n" "coma_bug\t: %s\n" "fpu\t\t: %s\n" Loading @@ -36,7 +35,6 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c) "cpuid level\t: %d\n" "wp\t\t: %s\n", c->fdiv_bug ? "yes" : "no", c->hlt_works_ok ? "no" : "yes", c->f00f_bug ? "yes" : "no", c->coma_bug ? "yes" : "no", c->hard_math ? "yes" : "no", Loading
arch/x86/kernel/process.c +6 −83 Original line number Diff line number Diff line Loading @@ -390,7 +390,8 @@ void default_idle(void) EXPORT_SYMBOL(default_idle); #endif bool set_pm_idle_to_default(void) #ifdef CONFIG_XEN bool xen_set_default_idle(void) { bool ret = !!x86_idle; Loading @@ -398,6 +399,7 @@ bool set_pm_idle_to_default(void) return ret; } #endif void stop_this_cpu(void *dummy) { local_irq_disable(); Loading @@ -407,32 +409,9 @@ void stop_this_cpu(void *dummy) set_cpu_online(smp_processor_id(), false); disable_local_APIC(); for (;;) { if (hlt_works(smp_processor_id())) for (;;) halt(); } } /* Default MONITOR/MWAIT with no hints, used for default C1 state */ static void mwait_idle(void) { if (!need_resched()) { trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle_rcuidle(1, smp_processor_id()); if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) clflush((void *)¤t_thread_info()->flags); __monitor((void *)¤t_thread_info()->flags, 0, 0); smp_mb(); if (!need_resched()) __sti_mwait(0, 0); else local_irq_enable(); trace_power_end_rcuidle(smp_processor_id()); trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); } else local_irq_enable(); } /* * On SMP it's slightly faster (but much more power-consuming!) Loading @@ -450,53 +429,6 @@ static void poll_idle(void) trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); } /* * mwait selection logic: * * It depends on the CPU. For AMD CPUs that support MWAIT this is * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings * then depend on a clock divisor and current Pstate of the core. If * all cores of a processor are in halt state (C1) the processor can * enter the C1E (C1 enhanced) state. If mwait is used this will never * happen. * * idle=mwait overrides this decision and forces the usage of mwait. */ #define MWAIT_INFO 0x05 #define MWAIT_ECX_EXTENDED_INFO 0x01 #define MWAIT_EDX_C1 0xf0 int mwait_usable(const struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; /* Use mwait if idle=mwait boot option is given */ if (boot_option_idle_override == IDLE_FORCE_MWAIT) return 1; /* * Any idle= boot option other than idle=mwait means that we must not * use mwait. Eg: idle=halt or idle=poll or idle=nomwait */ if (boot_option_idle_override != IDLE_NO_OVERRIDE) return 0; if (c->cpuid_level < MWAIT_INFO) return 0; cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); /* Check, whether EDX has extended info about MWAIT */ if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) return 1; /* * edx enumeratios MONITOR/MWAIT extensions. Check, whether * C1 supports MWAIT */ return (edx & MWAIT_EDX_C1); } bool amd_e400_c1e_detected; EXPORT_SYMBOL(amd_e400_c1e_detected); Loading Loading @@ -567,13 +499,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) if (x86_idle) return; if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { /* * One CPU supports mwait => All CPUs supports mwait */ pr_info("using mwait in idle threads\n"); x86_idle = mwait_idle; } else if (cpu_has_amd_erratum(amd_erratum_400)) { if (cpu_has_amd_erratum(amd_erratum_400)) { /* E400: APIC timer interrupt does not wake up CPU from C1e */ pr_info("using AMD E400 aware idle routine\n"); x86_idle = amd_e400_idle; Loading @@ -597,9 +523,6 @@ static int __init idle_setup(char *str) pr_info("using polling idle threads\n"); x86_idle = poll_idle; boot_option_idle_override = IDLE_POLL; } else if (!strcmp(str, "mwait")) { boot_option_idle_override = IDLE_FORCE_MWAIT; WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); } else if (!strcmp(str, "halt")) { /* * When the boot option of idle=halt is added, halt is Loading