Commit ca3f9d5d authored by Yicong Yang's avatar Yicong Yang Committed by Slim6882
Browse files

drivers/perf: hisi_pcie: Add more events for counting TLP bandwidth 

mainline inclusion
from mainline-v6.9-rc1
commit 00ca69b856ba5ff0dab241bafe7119cd08348a92
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I9HCSA
CVE: NA

Reference: https://lore.kernel.org/all/20240223103359.18669-1-yangyicong@huawei.com/



------------------------------------------------------------------------

A typical PCIe transaction is consisted of various TLP packets in both
direction. For counting bandwidth only memory read events are exported
currently. Add memory write and completion counting events of both
direction to complete the bandwidth counting.

Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20240223103359.18669-5-yangyicong@huawei.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarSlim6882 <yangjunshuo@huawei.com>
parent d3ffd8f5

drivers/perf/hisilicon/hisi_pcie_pmu.c

+8 −0
Original line number Diff line number Diff line
@@ -724,10 +724,18 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = { 
	HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011),

	HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_flux, 0x0104),

	HISI_PCIE_PMU_EVENT_ATTR(rx_mwr_time, 0x10104),

	HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804),

	HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804),

	HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_flux, 0x2004),

	HISI_PCIE_PMU_EVENT_ATTR(rx_cpl_time, 0x12004),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_flux, 0x0105),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mwr_time, 0x10105),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405),

	HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405),

	HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_flux, 0x1005),

	HISI_PCIE_PMU_EVENT_ATTR(tx_cpl_time, 0x11005),

	NULL

};