Commit ca295ffb authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Vineet Gupta
Browse files

arc: perf: Move static structs to where they're really used 



It is all well described by Stephen Rothwell who initially spotted that:
----------------------------->8----------------------------
After merging the origin tree, today's linux-next build (arc
haps_hs_smp_defconfig+kselftest) produced these warnings:

arch/arc/include/asm/perf_event.h:126:27: warning: 'arc_pmu_cache_map' defined but not used [-Wunused-const-variable=]
arch/arc/include/asm/perf_event.h:91:27: warning: 'arc_pmu_ev_hw_map' defined but not used [-Wunused-const-variable=]

Introduced by commit 0dd450fe ("ARC: Add perf support for ARC700 cores")

The 2 static arrays should be moved into arch/arc/kernel/perf_event.c
(the only place that uses them). We get the warning because perf_event.h
is also included by arch/arc/kernel/unaligned.c.
----------------------------->8----------------------------

Could be easily reproduced by running make with "W=1" on any up-to-date
sources, when extra warnings get enabled (in particular
"-Wunused-const-variable"), otherwise disabled by default in the top-level
Makefile as "These warnings generated too much noise in a regular build".

Cc: Mischa Jonker <mjonker@synopsys.com>
Reported-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@kernel.org>
parent 1b2a62be

arch/arc/include/asm/perf_event.h

+0 −162
Original line number Original line Diff line number Diff line
@@ -63,166 +63,4 @@ struct arc_reg_cc_build { 




#define PERF_COUNT_ARC_HW_MAX	(PERF_COUNT_HW_MAX + 8)

#define PERF_COUNT_ARC_HW_MAX	(PERF_COUNT_HW_MAX + 8)





/*

 * Some ARC pct quirks:

 *

 * PERF_COUNT_HW_STALLED_CYCLES_BACKEND

 * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND

 *	The ARC 700 can either measure stalls per pipeline stage, or all stalls

 *	combined; for now we assign all stalls to STALLED_CYCLES_BACKEND

 *	and all pipeline flushes (e.g. caused by mispredicts, etc.) to

 *	STALLED_CYCLES_FRONTEND.

 *

 *	We could start multiple performance counters and combine everything

 *	afterwards, but that makes it complicated.

 *

 *	Note that I$ cache misses aren't counted by either of the two!

 */



/*

 * ARC PCT has hardware conditions with fixed "names" but variable "indexes"

 * (based on a specific RTL build)

 * Below is the static map between perf generic/arc specific event_id and

 * h/w condition names.

 * At the time of probe, we loop thru each index and find it's name to

 * complete the mapping of perf event_id to h/w index as latter is needed

 * to program the counter really

 */

static const char * const arc_pmu_ev_hw_map[] = {

	/* count cycles */

	[PERF_COUNT_HW_CPU_CYCLES] = "crun",

	[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",

	[PERF_COUNT_HW_BUS_CYCLES] = "crun",



	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",

	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",



	/* counts condition */

	[PERF_COUNT_HW_INSTRUCTIONS] = "iall",

	/* All jump instructions that are taken */

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",

#ifdef CONFIG_ISA_ARCV2

	[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",

#else

	[PERF_COUNT_ARC_BPOK]         = "bpok",	  /* NP-NT, PT-T, PNT-NT */

	[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */

#endif

	[PERF_COUNT_ARC_LDC] = "imemrdc",	/* Instr: mem read cached */

	[PERF_COUNT_ARC_STC] = "imemwrc",	/* Instr: mem write cached */



	[PERF_COUNT_ARC_DCLM] = "dclm",		/* D-cache Load Miss */

	[PERF_COUNT_ARC_DCSM] = "dcsm",		/* D-cache Store Miss */

	[PERF_COUNT_ARC_ICM] = "icm",		/* I-cache Miss */

	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */

	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */



	[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",	/* Instr: mem read cached */

	[PERF_COUNT_HW_CACHE_MISSES] = "dclm",		/* D-cache Load Miss */

};



#define C(_x)			PERF_COUNT_HW_CACHE_##_x

#define CACHE_OP_UNSUPPORTED	0xffff



static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCLM,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_STC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCSM,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(L1I)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_HW_INSTRUCTIONS,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_ICM,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(LL)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(DTLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EDTLB,

		},

			/* DTLB LD/ST Miss not segregated by h/w*/

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EITLB,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,

			[C(RESULT_MISS)]	= PERF_COUNT_HW_BRANCH_MISSES,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(NODE)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

};



#endif /* __ASM_PERF_EVENT_H */
 
#endif /* __ASM_PERF_EVENT_H */

arch/arc/kernel/perf_event.c

+162 −0
Original line number Original line Diff line number Diff line
@@ -17,6 +17,168 @@ 
/* HW holds 8 symbols + one for null terminator */

/* HW holds 8 symbols + one for null terminator */

#define ARCPMU_EVENT_NAME_LEN	9

#define ARCPMU_EVENT_NAME_LEN	9





/*

 * Some ARC pct quirks:

 *

 * PERF_COUNT_HW_STALLED_CYCLES_BACKEND

 * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND

 *	The ARC 700 can either measure stalls per pipeline stage, or all stalls

 *	combined; for now we assign all stalls to STALLED_CYCLES_BACKEND

 *	and all pipeline flushes (e.g. caused by mispredicts, etc.) to

 *	STALLED_CYCLES_FRONTEND.

 *

 *	We could start multiple performance counters and combine everything

 *	afterwards, but that makes it complicated.

 *

 *	Note that I$ cache misses aren't counted by either of the two!

 */



/*

 * ARC PCT has hardware conditions with fixed "names" but variable "indexes"

 * (based on a specific RTL build)

 * Below is the static map between perf generic/arc specific event_id and

 * h/w condition names.

 * At the time of probe, we loop thru each index and find it's name to

 * complete the mapping of perf event_id to h/w index as latter is needed

 * to program the counter really

 */

static const char * const arc_pmu_ev_hw_map[] = {

	/* count cycles */

	[PERF_COUNT_HW_CPU_CYCLES] = "crun",

	[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",

	[PERF_COUNT_HW_BUS_CYCLES] = "crun",



	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",

	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",



	/* counts condition */

	[PERF_COUNT_HW_INSTRUCTIONS] = "iall",

	/* All jump instructions that are taken */

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",

#ifdef CONFIG_ISA_ARCV2

	[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",

#else

	[PERF_COUNT_ARC_BPOK]         = "bpok",	  /* NP-NT, PT-T, PNT-NT */

	[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */

#endif

	[PERF_COUNT_ARC_LDC] = "imemrdc",	/* Instr: mem read cached */

	[PERF_COUNT_ARC_STC] = "imemwrc",	/* Instr: mem write cached */



	[PERF_COUNT_ARC_DCLM] = "dclm",		/* D-cache Load Miss */

	[PERF_COUNT_ARC_DCSM] = "dcsm",		/* D-cache Store Miss */

	[PERF_COUNT_ARC_ICM] = "icm",		/* I-cache Miss */

	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */

	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */



	[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",	/* Instr: mem read cached */

	[PERF_COUNT_HW_CACHE_MISSES] = "dclm",		/* D-cache Load Miss */

};



#define C(_x)			PERF_COUNT_HW_CACHE_##_x

#define CACHE_OP_UNSUPPORTED	0xffff



static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCLM,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_STC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCSM,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(L1I)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_HW_INSTRUCTIONS,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_ICM,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(LL)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(DTLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EDTLB,

		},

			/* DTLB LD/ST Miss not segregated by h/w*/

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EITLB,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,

			[C(RESULT_MISS)]	= PERF_COUNT_HW_BRANCH_MISSES,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

	[C(NODE)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,

		},

	},

};



enum arc_pmu_attr_groups {

enum arc_pmu_attr_groups {

	ARCPMU_ATTR_GR_EVENTS,

	ARCPMU_ATTR_GR_EVENTS,

	ARCPMU_ATTR_GR_FORMATS,

	ARCPMU_ATTR_GR_FORMATS,