Commit ca0fdfd1 authored by Alim Akhtar's avatar Alim Akhtar Committed by Krzysztof Kozlowski
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clk: samsung: fsd: Add cmu_imem block clock information 



Adds cmu_imem clock related code, imem block contains IPs
like WDT, DMA, TMU etc, these clocks are required for such
IP function.

Cc: linux-fsd@tesla.com
Signed-off-by: default avatarArjun K V <arjun.kv@samsung.com>
Signed-off-by: default avatarPankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: default avatarTauseef Nomani <tauseef.n@samsung.com>
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-9-alim.akhtar@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
parent bfbce52e

drivers/clk/samsung/clk-fsd.c

+283 −0
Original line number Diff line number Diff line
@@ -1144,6 +1144,289 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 
	.clk_name		= "dout_cmu_fsys1_shared0div4",

};



/* Register Offset definitions for CMU_IMEM (0x10010000) */

#define PLL_CON0_CLK_IMEM_ACLK				0x100

#define PLL_CON0_CLK_IMEM_INTMEMCLK			0x120

#define PLL_CON0_CLK_IMEM_TCUCLK			0x140

#define DIV_OSCCLK_IMEM_TMUTSCLK			0x1800

#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK		0x2000

#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO		0x2004

#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK		0x2008

#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK		0x200c

#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK		0x2010

#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS		0x2014

#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK		0x2018

#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS		0x201c

#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK		0x2020

#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS		0x2024

#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK			0x2028

#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS		0x202c

#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK		0x2030

#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS		0x2034

#define GAT_IMEM_WDT0_IPCLKPORT_CLK			0x2038

#define GAT_IMEM_WDT1_IPCLKPORT_CLK			0x203c

#define GAT_IMEM_WDT2_IPCLKPORT_CLK			0x2040

#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM	0x2044

#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM	0x2048

#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM	0x204c

#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS	0x2050

#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS	0x2054

#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS	0x2058

#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM		0x205c

#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS		0x2060

#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM		0x2064

#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS		0x2068

#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK		0x206c

#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK		0x2070

#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK		0x2074

#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK		0x2078

#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK		0x207c

#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK		0x2080

#define GAT_IMEM_DMA0_IPCLKPORT_ACLK			0x2084

#define GAT_IMEM_DMA1_IPCLKPORT_ACLK			0x2088

#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK	0x208c

#define GAT_IMEM_GIC_IPCLKPORT_CLK			0x2090

#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK			0x2094

#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK	0x2098

#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK	0x209c

#define GAT_IMEM_MCT_IPCLKPORT_PCLK			0x20a0

#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D	0x20a4

#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU	0x20a8

#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P	0x20ac

#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK		0x20b0

#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK		0x20b4

#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK	0x20b8

#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK		0x20bc

#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK		0x20c0

#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK		0x20c4

#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK		0x20c8

#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK		0x20cc

#define GAT_IMEM_TCU_IPCLKPORT_ACLK			0x20d0

#define GAT_IMEM_WDT0_IPCLKPORT_PCLK			0x20d4

#define GAT_IMEM_WDT1_IPCLKPORT_PCLK			0x20d8

#define GAT_IMEM_WDT2_IPCLKPORT_PCLK			0x20dc



static const unsigned long imem_clk_regs[] __initconst = {

	PLL_CON0_CLK_IMEM_ACLK,

	PLL_CON0_CLK_IMEM_INTMEMCLK,

	PLL_CON0_CLK_IMEM_TCUCLK,

	DIV_OSCCLK_IMEM_TMUTSCLK,

	GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,

	GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,

	GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,

	GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,

	GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,

	GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,

	GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,

	GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,

	GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,

	GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,

	GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,

	GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,

	GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,

	GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,

	GAT_IMEM_WDT0_IPCLKPORT_CLK,

	GAT_IMEM_WDT1_IPCLKPORT_CLK,

	GAT_IMEM_WDT2_IPCLKPORT_CLK,

	GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,

	GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,

	GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,

	GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,

	GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,

	GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,

	GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,

	GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,

	GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,

	GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,

	GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,

	GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,

	GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,

	GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,

	GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,

	GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,

	GAT_IMEM_DMA0_IPCLKPORT_ACLK,

	GAT_IMEM_DMA1_IPCLKPORT_ACLK,

	GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,

	GAT_IMEM_GIC_IPCLKPORT_CLK,

	GAT_IMEM_INTMEM_IPCLKPORT_ACLK,

	GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,

	GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,

	GAT_IMEM_MCT_IPCLKPORT_PCLK,

	GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,

	GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,

	GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,

	GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,

	GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,

	GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,

	GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,

	GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,

	GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,

	GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,

	GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,

	GAT_IMEM_TCU_IPCLKPORT_ACLK,

	GAT_IMEM_WDT0_IPCLKPORT_PCLK,

	GAT_IMEM_WDT1_IPCLKPORT_PCLK,

	GAT_IMEM_WDT2_IPCLKPORT_PCLK,

};



PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };

PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };

PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };



static const struct samsung_mux_clock imem_mux_clks[] __initconst = {

	MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,

	    PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),

	MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),

	MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,

	    PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),

};



static const struct samsung_div_clock imem_div_clks[] __initconst = {

	DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),

};



static const struct samsung_gate_clock imem_gate_clks[] __initconst = {

	GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",

	     GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",

	     GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",

	     GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",

	     GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",

	     GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",

	     GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",

	     GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",

	     GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",

	     GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",

	     "dout_imem_oscclk_imem_tmutsclk",

	     GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",

	     "dout_imem_oscclk_imem_tmutsclk",

	     GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",

	     "dout_imem_oscclk_imem_tmutsclk",

	     GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",

	     "dout_imem_oscclk_imem_tmutsclk",

	     GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",

	     "dout_imem_oscclk_imem_tmutsclk",

	     GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),

	GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),

	GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",

	     GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",

	     "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",

	     "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,

	     CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",

	     GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",

	     GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",

	     GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",

	     GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

	GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",

	     GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),

};



static const struct samsung_cmu_info imem_cmu_info __initconst = {

	.mux_clks		= imem_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(imem_mux_clks),

	.div_clks		= imem_div_clks,

	.nr_div_clks		= ARRAY_SIZE(imem_div_clks),

	.gate_clks		= imem_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),

	.nr_clk_ids		= IMEM_NR_CLK,

	.clk_regs		= imem_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),

};



static void __init fsd_clk_imem_init(struct device_node *np)

{

	samsung_cmu_register_one(np, &imem_cmu_info);

}



CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);



/**

 * fsd_cmu_probe - Probe function for FSD platform clocks

 * @pdev: Pointer to platform device