Commit c9dc03dd authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge tag 'marvell-xor-cleanup-dt-binding-3.8' of... 

Merge tag 'marvell-xor-cleanup-dt-binding-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything

Marvell XOR driver cleanup and DT binding for 3.8
parents 61528f4e 34c93c86

Documentation/devicetree/bindings/dma/mv-xor.txt

0 → 100644
+40 −0
Original line number Diff line number Diff line 
* Marvell XOR engines



Required properties:

- compatible: Should be "marvell,orion-xor"

- reg: Should contain registers location and length (two sets)

    the first set is the low registers, the second set the high

    registers for the XOR engine.

- clocks: pointer to the reference clock



The DT node must also contains sub-nodes for each XOR channel that the

XOR engine has. Those sub-nodes have the following required

properties:

- interrupts: interrupt of the XOR channel



And the following optional properties:

- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations

- dmacap,memset to indicate that the XOR channel is capable of memset operations

- dmacap,xor to indicate that the XOR channel is capable of xor operations



Example:



xor@d0060900 {

	compatible = "marvell,orion-xor";

	reg = <0xd0060900 0x100

	       0xd0060b00 0x100>;

	clocks = <&coreclk 0>;

	status = "okay";



	xor00 {

	      interrupts = <51>;

	      dmacap,memcpy;

	      dmacap,xor;

	};

	xor01 {

	      interrupts = <52>;

	      dmacap,memcpy;

	      dmacap,xor;

	      dmacap,memset;

	};

};

arch/arm/mach-dove/common.c

+5 −4
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include <linux/irq.h>

#include <plat/time.h>

#include <linux/platform_data/usb-ehci-orion.h>

#include <linux/platform_data/dma-mv_xor.h>

#include <plat/irq.h>

#include <plat/common.h>

#include <plat/addr-map.h>
@@ -124,8 +125,8 @@ static void __init dove_clk_init(void) 
	orion_clkdev_add(NULL, "mv_crypto", crypto);

	orion_clkdev_add(NULL, "dove-ac97", ac97);

	orion_clkdev_add(NULL, "dove-pdma", pdma);

	orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);

	orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);

	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);

	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);

}



/*****************************************************************************
@@ -410,11 +411,11 @@ static void __init dove_legacy_clk_init(void) 
			 of_clk_get_from_provider(&clkspec));



	clkspec.args[0] = CLOCK_GATING_BIT_XOR0;

	orion_clkdev_add(NULL, "mv_xor_shared.0",

	orion_clkdev_add(NULL, MV_XOR_NAME ".0",

			 of_clk_get_from_provider(&clkspec));



	clkspec.args[0] = CLOCK_GATING_BIT_XOR1;

	orion_clkdev_add(NULL, "mv_xor_shared.1",

	orion_clkdev_add(NULL, MV_XOR_NAME ".1",

			 of_clk_get_from_provider(&clkspec));

}

arch/arm/mach-kirkwood/board-dt.c

+3 −2
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <asm/mach/map.h>

#include <mach/bridge-regs.h>

#include <linux/platform_data/usb-ehci-orion.h>

#include <linux/platform_data/dma-mv_xor.h>

#include <plat/irq.h>

#include <plat/common.h>

#include "common.h"
@@ -60,11 +61,11 @@ static void __init kirkwood_legacy_clk_init(void) 
			 of_clk_get_from_provider(&clkspec));



	clkspec.args[0] = CGC_BIT_XOR0;

	orion_clkdev_add(NULL, "mv_xor_shared.0",

	orion_clkdev_add(NULL, MV_XOR_NAME ".0",

			 of_clk_get_from_provider(&clkspec));



	clkspec.args[0] = CGC_BIT_XOR1;

	orion_clkdev_add(NULL, "mv_xor_shared.1",

	orion_clkdev_add(NULL, MV_XOR_NAME ".1",

			 of_clk_get_from_provider(&clkspec));



	clkspec.args[0] = CGC_BIT_PEX1;

arch/arm/mach-kirkwood/common.c

+2 −2
Original line number Diff line number Diff line
@@ -260,8 +260,8 @@ void __init kirkwood_clk_init(void) 
	orion_clkdev_add(NULL, "orion_nand", runit);

	orion_clkdev_add(NULL, "mvsdio", sdio);

	orion_clkdev_add(NULL, "mv_crypto", crypto);

	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);

	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);

	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);

	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);

	orion_clkdev_add("0", "pcie", pex0);

	orion_clkdev_add("1", "pcie", pex1);

	orion_clkdev_add(NULL, "kirkwood-i2s", audio);

arch/arm/plat-orion/common.c

+63 −129
Original line number Diff line number Diff line
@@ -606,26 +606,6 @@ void __init orion_wdt_init(void) 
 ****************************************************************************/

static u64 orion_xor_dmamask = DMA_BIT_MASK(32);



void __init orion_xor_init_channels(

	struct mv_xor_platform_data *orion_xor0_data,

	struct platform_device *orion_xor0_channel,

	struct mv_xor_platform_data *orion_xor1_data,

	struct platform_device *orion_xor1_channel)

{

	/*

	 * two engines can't do memset simultaneously, this limitation

	 * satisfied by removing memset support from one of the engines.

	 */

	dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);

	dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);

	platform_device_register(orion_xor0_channel);



	dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);

	dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);

	dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);

	platform_device_register(orion_xor1_channel);

}



/*****************************************************************************

 * XOR0

 ****************************************************************************/
@@ -636,61 +616,30 @@ static struct resource orion_xor0_shared_resources[] = { 
	}, {

		.name	= "xor 0 high",

		.flags	= IORESOURCE_MEM,

	},

};



static struct platform_device orion_xor0_shared = {

	.name		= MV_XOR_SHARED_NAME,

	.id		= 0,

	.num_resources	= ARRAY_SIZE(orion_xor0_shared_resources),

	.resource	= orion_xor0_shared_resources,

};



static struct resource orion_xor00_resources[] = {

	[0] = {

	}, {

		.name   = "irq channel 0",

		.flags  = IORESOURCE_IRQ,

	},

};



static struct mv_xor_platform_data orion_xor00_data = {

	.shared		= &orion_xor0_shared,

	.hw_id		= 0,

	.pool_size	= PAGE_SIZE,

};



static struct platform_device orion_xor00_channel = {

	.name		= MV_XOR_NAME,

	.id		= 0,

	.num_resources	= ARRAY_SIZE(orion_xor00_resources),

	.resource	= orion_xor00_resources,

	.dev		= {

		.dma_mask		= &orion_xor_dmamask,

		.coherent_dma_mask	= DMA_BIT_MASK(64),

		.platform_data		= &orion_xor00_data,

	},

};



static struct resource orion_xor01_resources[] = {

	[0] = {

	}, {

		.name   = "irq channel 1",

		.flags  = IORESOURCE_IRQ,

	},

};



static struct mv_xor_platform_data orion_xor01_data = {

	.shared		= &orion_xor0_shared,

	.hw_id		= 1,

	.pool_size	= PAGE_SIZE,

static struct mv_xor_channel_data orion_xor0_channels_data[2];



static struct mv_xor_platform_data orion_xor0_pdata = {

	.channels = orion_xor0_channels_data,

};



static struct platform_device orion_xor01_channel = {

static struct platform_device orion_xor0_shared = {

	.name		= MV_XOR_NAME,

	.id		= 1,

	.num_resources	= ARRAY_SIZE(orion_xor01_resources),

	.resource	= orion_xor01_resources,

	.id		= 0,

	.num_resources	= ARRAY_SIZE(orion_xor0_shared_resources),

	.resource	= orion_xor0_shared_resources,

	.dev            = {

		.dma_mask               = &orion_xor_dmamask,

		.coherent_dma_mask      = DMA_BIT_MASK(64),

		.platform_data		= &orion_xor01_data,

		.platform_data          = &orion_xor0_pdata,

	},

};
@@ -704,15 +653,23 @@ void __init orion_xor0_init(unsigned long mapbase_low, 
	orion_xor0_shared_resources[1].start = mapbase_high;

	orion_xor0_shared_resources[1].end = mapbase_high + 0xff;



	orion_xor00_resources[0].start = irq_0;

	orion_xor00_resources[0].end = irq_0;

	orion_xor01_resources[0].start = irq_1;

	orion_xor01_resources[0].end = irq_1;

	orion_xor0_shared_resources[2].start = irq_0;

	orion_xor0_shared_resources[2].end = irq_0;

	orion_xor0_shared_resources[3].start = irq_1;

	orion_xor0_shared_resources[3].end = irq_1;



	platform_device_register(&orion_xor0_shared);

	/*

	 * two engines can't do memset simultaneously, this limitation

	 * satisfied by removing memset support from one of the engines.

	 */

	dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);

	dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);



	dma_cap_set(DMA_MEMSET, orion_xor0_channels_data[1].cap_mask);

	dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);

	dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);



	orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,

				&orion_xor01_data, &orion_xor01_channel);

	platform_device_register(&orion_xor0_shared);

}



/*****************************************************************************
@@ -725,61 +682,30 @@ static struct resource orion_xor1_shared_resources[] = { 
	}, {

		.name	= "xor 1 high",

		.flags	= IORESOURCE_MEM,

	},

};



static struct platform_device orion_xor1_shared = {

	.name		= MV_XOR_SHARED_NAME,

	.id		= 1,

	.num_resources	= ARRAY_SIZE(orion_xor1_shared_resources),

	.resource	= orion_xor1_shared_resources,

};



static struct resource orion_xor10_resources[] = {

	[0] = {

	}, {

		.name   = "irq channel 0",

		.flags  = IORESOURCE_IRQ,

	},

};



static struct mv_xor_platform_data orion_xor10_data = {

	.shared		= &orion_xor1_shared,

	.hw_id		= 0,

	.pool_size	= PAGE_SIZE,

};



static struct platform_device orion_xor10_channel = {

	.name		= MV_XOR_NAME,

	.id		= 2,

	.num_resources	= ARRAY_SIZE(orion_xor10_resources),

	.resource	= orion_xor10_resources,

	.dev		= {

		.dma_mask		= &orion_xor_dmamask,

		.coherent_dma_mask	= DMA_BIT_MASK(64),

		.platform_data		= &orion_xor10_data,

	},

};



static struct resource orion_xor11_resources[] = {

	[0] = {

	}, {

		.name   = "irq channel 1",

		.flags  = IORESOURCE_IRQ,

	},

};



static struct mv_xor_platform_data orion_xor11_data = {

	.shared		= &orion_xor1_shared,

	.hw_id		= 1,

	.pool_size	= PAGE_SIZE,

static struct mv_xor_channel_data orion_xor1_channels_data[2];



static struct mv_xor_platform_data orion_xor1_pdata = {

	.channels = orion_xor1_channels_data,

};



static struct platform_device orion_xor11_channel = {

static struct platform_device orion_xor1_shared = {

	.name		= MV_XOR_NAME,

	.id		= 3,

	.num_resources	= ARRAY_SIZE(orion_xor11_resources),

	.resource	= orion_xor11_resources,

	.id		= 1,

	.num_resources	= ARRAY_SIZE(orion_xor1_shared_resources),

	.resource	= orion_xor1_shared_resources,

	.dev            = {

		.dma_mask               = &orion_xor_dmamask,

		.coherent_dma_mask      = DMA_BIT_MASK(64),

		.platform_data		= &orion_xor11_data,

		.platform_data          = &orion_xor1_pdata,

	},

};
@@ -793,15 +719,23 @@ void __init orion_xor1_init(unsigned long mapbase_low, 
	orion_xor1_shared_resources[1].start = mapbase_high;

	orion_xor1_shared_resources[1].end = mapbase_high + 0xff;



	orion_xor10_resources[0].start = irq_0;

	orion_xor10_resources[0].end = irq_0;

	orion_xor11_resources[0].start = irq_1;

	orion_xor11_resources[0].end = irq_1;

	orion_xor1_shared_resources[2].start = irq_0;

	orion_xor1_shared_resources[2].end = irq_0;

	orion_xor1_shared_resources[3].start = irq_1;

	orion_xor1_shared_resources[3].end = irq_1;



	platform_device_register(&orion_xor1_shared);

	/*

	 * two engines can't do memset simultaneously, this limitation

	 * satisfied by removing memset support from one of the engines.

	 */

	dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);

	dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);



	orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,

				&orion_xor11_data, &orion_xor11_channel);

	dma_cap_set(DMA_MEMSET, orion_xor1_channels_data[1].cap_mask);

	dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);

	dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);



	platform_device_register(&orion_xor1_shared);

}



/*****************************************************************************