Commit c97ffd08 authored by John Harrison's avatar John Harrison Committed by Chris Wilson
Browse files

drm/i915: Correct location of Wa_1408615072 



The above workaround was added as an engine workaround not a GT
workaround. Moved it to the correct location.

Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201210170615.3107266-1-lucas.demarchi@intel.com
parent d0d829e5

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −4
Original line number Diff line number Diff line
@@ -1279,6 +1279,11 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		wa_write_or(wal,

			    SLICE_UNIT_LEVEL_CLKGATE,

			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);



	/* Wa_1408615072:tgl[a0] */

	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))

		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,

			    VSUNIT_CLKGATE_DIS_TGL);

}



static void
@@ -1771,10 +1776,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
		wa_write_or(wal,

			    GEN7_SARCHKMD,

			    GEN7_DISABLE_SAMPLER_PREFETCH);



		/* Wa_1408615072:tgl */

		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,

			    VSUNIT_CLKGATE_DIS_TGL);

	}



	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {