Commit c94a9aab authored by Daniel Golle's avatar Daniel Golle Committed by Jakub Kicinski
Browse files

dt-bindings: net: mediatek,net: add mt7988-eth binding 



Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml.
The MT7988 SoC got 3 Ethernet MACs operating at a maximum of
10 Gigabit/sec supported by 2 packet processor engines for
offloading tasks.
The first MAC is hard-wired to a built-in switch which exposes
four 1000Base-T PHYs as user ports.
It also comes with built-in 2500Base-T PHY which can be used
with the 2nd GMAC.
The 2nd and 3rd GMAC can be connected to external PHYs or provide
SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII,
5GBase-KR or 10GBase-KR.

Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/3c83d2c0d629dac064ec4396132538c52e77a57f.1690246066.git.daniel@makrotopia.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 1cbf487d

Documentation/devicetree/bindings/net/mediatek,net.yaml

+76 −6
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ properties: 
      - mediatek,mt7629-eth

      - mediatek,mt7981-eth

      - mediatek,mt7986-eth

      - mediatek,mt7988-eth

      - ralink,rt5350-eth



  reg:
@@ -61,6 +62,12 @@ properties: 
      Phandle to the mediatek hifsys controller used to provide various clocks

      and reset to the system.



  mediatek,infracfg:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon node that handles the path from GMAC to

      PHY variants.



  mediatek,sgmiisys:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    minItems: 1
@@ -122,6 +129,8 @@ allOf: 
            - const: gp1

            - const: gp2



        mediatek,infracfg: false



        mediatek,pctl:

          $ref: /schemas/types.yaml#/definitions/phandle

          description:
@@ -152,6 +161,8 @@ allOf: 
            - const: ethif

            - const: fe



        mediatek,infracfg: false



        mediatek,wed: false



        mediatek,wed-pcie: false
@@ -184,6 +195,8 @@ allOf: 
            - const: sgmii_ck

            - const: eth2pll



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 1

          maxItems: 1
@@ -229,12 +242,6 @@ allOf: 
            - const: sgmii_ck

            - const: eth2pll



        mediatek,infracfg:

          $ref: /schemas/types.yaml#/definitions/phandle

          description:

            Phandle to the syscon node that handles the path from GMAC to

            PHY variants.



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2
@@ -275,6 +282,8 @@ allOf: 
            - const: netsys0

            - const: netsys1



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2
@@ -311,6 +320,67 @@ allOf: 
            - const: netsys0

            - const: netsys1



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2



  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt7988-eth

    then:

      properties:

        interrupts:

          minItems: 4



        clocks:

          minItems: 34

          maxItems: 34



        clock-names:

          items:

            - const: crypto

            - const: fe

            - const: gp2

            - const: gp1

            - const: gp3

            - const: ethwarp_wocpu2

            - const: ethwarp_wocpu1

            - const: ethwarp_wocpu0

            - const: esw

            - const: netsys0

            - const: netsys1

            - const: sgmii_tx250m

            - const: sgmii_rx250m

            - const: sgmii2_tx250m

            - const: sgmii2_rx250m

            - const: top_usxgmii0_sel

            - const: top_usxgmii1_sel

            - const: top_sgm0_sel

            - const: top_sgm1_sel

            - const: top_xfi_phy0_xtal_sel

            - const: top_xfi_phy1_xtal_sel

            - const: top_eth_gmii_sel

            - const: top_eth_refck_50m_sel

            - const: top_eth_sys_200m_sel

            - const: top_eth_sys_sel

            - const: top_eth_xgmii_sel

            - const: top_eth_mii_sel

            - const: top_netsys_sel

            - const: top_netsys_500m_sel

            - const: top_netsys_pao_2x_sel

            - const: top_netsys_sync_250m_sel

            - const: top_netsys_ppefb_250m_sel

            - const: top_netsys_warp_sel

            - const: wocpu1

            - const: wocpu0

            - const: xgp1

            - const: xgp2

            - const: xgp3



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2