Commit c9424fa1 authored by Chris Wilson's avatar Chris Wilson Committed by Andi Shyti
Browse files

drm/i915/gt: Explicitly clear BB_OFFSET for new contexts 



Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.

Testcase: igt/i915_selftests/gt_lrc

v2:
  Extend it for gen8.
v3:
  BB_OFFSET is recorded per engine from Gen9 onwards

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarThomas Hellstrom <thomas.hellstrom@linux.intel.com>
Signed-off-by: default avatarKarolina Drobnik <karolina.drobnik@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/37c67abb3303852f06a570a4360addf52bf941c1.1663081418.git.karolina.drobnik@intel.com
parent 69a3738b

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ 
#define RING_SBBSTATE(base)			_MMIO((base) + 0x118) /* hsw+ */

#define RING_SBBADDR_UDW(base)			_MMIO((base) + 0x11c) /* gen8+ */

#define RING_BBADDR(base)			_MMIO((base) + 0x140)

#define RING_BB_OFFSET(base)			_MMIO((base) + 0x158)

#define RING_BBADDR_UDW(base)			_MMIO((base) + 0x168) /* gen8+ */

#define CCID(base)				_MMIO((base) + 0x180)

#define   CCID_EN				BIT(0)

drivers/gpu/drm/i915/gt/intel_lrc.c

+20 −0
Original line number Diff line number Diff line
@@ -662,6 +662,21 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) 
		return -1;

}



static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)

{

	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))

		return 0x80;

	else if (GRAPHICS_VER(engine->i915) >= 12)

		return 0x70;

	else if (GRAPHICS_VER(engine->i915) >= 9)

		return 0x64;

	else if (GRAPHICS_VER(engine->i915) >= 8 &&

		 engine->class == RENDER_CLASS)

		return 0xc4;

	else

		return -1;

}



static int lrc_ring_gpr0(const struct intel_engine_cs *engine)

{

	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -768,6 +783,7 @@ static void init_common_regs(u32 * const regs, 
			     bool inhibit)

{

	u32 ctl;

	int loc;



	ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);

	ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
@@ -779,6 +795,10 @@ static void init_common_regs(u32 * const regs, 
	regs[CTX_CONTEXT_CONTROL] = ctl;



	regs[CTX_TIMESTAMP] = ce->stats.runtime.last;



	loc = lrc_ring_bb_offset(engine);

	if (loc != -1)

		regs[loc + 1] = 0;

}



static void init_wa_bb_regs(u32 * const regs,

drivers/gpu/drm/i915/gt/selftest_lrc.c

+5 −0
Original line number Diff line number Diff line
@@ -357,6 +357,11 @@ static int live_lrc_fixed(void *arg) 
				lrc_ring_cmd_buf_cctl(engine),

				"RING_CMD_BUF_CCTL"

			},

			{

				i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),

				lrc_ring_bb_offset(engine),

				"RING_BB_OFFSET"

			},

			{ },

		}, *t;

		u32 *hw;