Commit c938aed8 authored Sep 29, 2021 by Nicholas Kazlauskas Committed by Alex Deucher Oct 20, 2021

drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1



[Why]
Prefetch BW calculated is lower than the DML reference because of a
porting error that's excluding cursor and row bandwidth from the
pixel data bandwidth.

[How]
Change the dml_max4 to dml_max3 and include cursor and row bandwidth
in the same calculation as the rest of the pixel data during vactive.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

parent c21b1053

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -5398,9 +5398,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l

		v->MaximumReadBandwidthWithPrefetch =
		v->MaximumReadBandwidthWithPrefetch
		+ dml_max4(
		v->VActivePixelBandwidth[i][j][k],
		v->VActiveCursorBandwidth[i][j][k]
		+ dml_max3(
		v->VActivePixelBandwidth[i][j][k]
		+ v->VActiveCursorBandwidth[i][j][k]
		+ v->NoOfDPP[i][j][k]
		* (v->meta_row_bandwidth[i][j][k]
		+ v->dpte_row_bandwidth[i][j][k]),